lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "mips-disassembler"
  28
  29 typedef MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 namespace {
  32
  33 class MipsDisassembler : public MCDisassembler {
  34   bool IsMicroMips;
  35   bool IsBigEndian;
  36 public:
  37   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
  38       : MCDisassembler(STI, Ctx),
  39         IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
  40         IsBigEndian(IsBigEndian) {}
  41
  42   bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
  43   bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
  44   bool hasMips32r6() const {
  45     return STI.getFeatureBits()[Mips::FeatureMips32r6];
  46   }
  47
  48   bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
  49
  50   bool hasCOP3() const {
  51     // Only present in MIPS-I and MIPS-II
  52     return !hasMips32() && !hasMips3();
  53   }
  54
  55   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  56                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  57                               raw_ostream &VStream,
  58                               raw_ostream &CStream) const override;
  59 };
  60
  61 } // end anonymous namespace
  62
  63 // Forward declare these because the autogenerated code will reference them.
  64 // Definitions are further down.
  65 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  66                                              unsigned RegNo,
  67                                              uint64_t Address,
  68                                              const void *Decoder);
  69
  70 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
  71                                                  unsigned RegNo,
  72                                                  uint64_t Address,
  73                                                  const void *Decoder);
  74
  75 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
  76                                                unsigned RegNo,
  77                                                uint64_t Address,
  78                                                const void *Decoder);
  79
  80 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
  81                                                    unsigned RegNo,
  82                                                    uint64_t Address,
  83                                                    const void *Decoder);
  84
  85 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
  86                                                     unsigned RegNo,
  87                                                     uint64_t Address,
  88                                                     const void *Decoder);
  89
  90 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
  91                                              unsigned RegNo,
  92                                              uint64_t Address,
  93                                              const void *Decoder);
  94
  95 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
  96                                            unsigned Insn,
  97                                            uint64_t Address,
  98                                            const void *Decoder);
  99
 100 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 101                                             unsigned RegNo,
 102                                             uint64_t Address,
 103                                             const void *Decoder);
 104
 105 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 106                                              unsigned RegNo,
 107                                              uint64_t Address,
 108                                              const void *Decoder);
 109
 110 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 111                                              unsigned RegNo,
 112                                              uint64_t Address,
 113                                              const void *Decoder);
 114
 115 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 116                                            unsigned RegNo,
 117                                            uint64_t Address,
 118                                            const void *Decoder);
 119
 120 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 121                                            unsigned RegNo,
 122                                            uint64_t Address,
 123                                            const void *Decoder);
 124
 125 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 126                                              uint64_t Address,
 127                                              const void *Decoder);
 128
 129 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 130                                               unsigned Insn,
 131                                               uint64_t Address,
 132                                               const void *Decoder);
 133
 134 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 135                                               unsigned RegNo,
 136                                               uint64_t Address,
 137                                               const void *Decoder);
 138
 139 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 140                                                 unsigned RegNo,
 141                                                 uint64_t Address,
 142                                                 const void *Decoder);
 143
 144 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 145                                                unsigned RegNo,
 146                                                uint64_t Address,
 147                                                const void *Decoder);
 148
 149 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 150                                                unsigned RegNo,
 151                                                uint64_t Address,
 152                                                const void *Decoder);
 153
 154 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 155                                                unsigned RegNo,
 156                                                uint64_t Address,
 157                                                const void *Decoder);
 158
 159 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 160                                                unsigned RegNo,
 161                                                uint64_t Address,
 162                                                const void *Decoder);
 163
 164 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 165                                                unsigned RegNo,
 166                                                uint64_t Address,
 167                                                const void *Decoder);
 168
 169 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 170                                                unsigned RegNo,
 171                                                uint64_t Address,
 172                                                const void *Decoder);
 173
 174 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 175                                                unsigned RegNo,
 176                                                uint64_t Address,
 177                                                const void *Decoder);
 178
 179 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 180                                             unsigned RegNo,
 181                                             uint64_t Address,
 182                                             const void *Decoder);
 183
 184 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 185                                        unsigned Offset,
 186                                        uint64_t Address,
 187                                        const void *Decoder);
 188
 189 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 190                                      unsigned Insn,
 191                                      uint64_t Address,
 192                                      const void *Decoder);
 193
 194 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 195                                          unsigned Offset,
 196                                          uint64_t Address,
 197                                          const void *Decoder);
 198
 199 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 200                                          unsigned Offset,
 201                                          uint64_t Address,
 202                                          const void *Decoder);
 203
 204 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
 205 // shifted left by 1 bit.
 206 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
 207                                           unsigned Offset,
 208                                           uint64_t Address,
 209                                           const void *Decoder);
 210
 211 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
 212 // shifted left by 1 bit.
 213 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
 214                                            unsigned Offset,
 215                                            uint64_t Address,
 216                                            const void *Decoder);
 217
 218 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 219 // shifted left by 1 bit.
 220 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 221                                          unsigned Offset,
 222                                          uint64_t Address,
 223                                          const void *Decoder);
 224
 225 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 226 // shifted left by 1 bit.
 227 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 228                                        unsigned Insn,
 229                                        uint64_t Address,
 230                                        const void *Decoder);
 231
 232 static DecodeStatus DecodeMem(MCInst &Inst,
 233                               unsigned Insn,
 234                               uint64_t Address,
 235                               const void *Decoder);
 236
 237 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 238                               unsigned Insn,
 239                               uint64_t Address,
 240                               const void *Decoder);
 241
 242 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
 243                                     unsigned Insn,
 244                                     uint64_t Address,
 245                                     const void *Decoder);
 246
 247 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
 248                                     unsigned Insn,
 249                                     uint64_t Address,
 250                                     const void *Decoder);
 251
 252 static DecodeStatus DecodeSyncI(MCInst &Inst,
 253                                 unsigned Insn,
 254                                 uint64_t Address,
 255                                 const void *Decoder);
 256
 257 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 258                                     uint64_t Address, const void *Decoder);
 259
 260 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
 261                                     unsigned Insn,
 262                                     uint64_t Address,
 263                                     const void *Decoder);
 264
 265 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
 266                                           unsigned Insn,
 267                                           uint64_t Address,
 268                                           const void *Decoder);
 269
 270 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
 271                                           unsigned Insn,
 272                                           uint64_t Address,
 273                                           const void *Decoder);
 274
 275 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
 276                                                unsigned Insn,
 277                                                uint64_t Address,
 278                                                const void *Decoder);
 279
 280 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 281                                      unsigned Insn,
 282                                      uint64_t Address,
 283                                      const void *Decoder);
 284
 285 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 286                                      unsigned Insn,
 287                                      uint64_t Address,
 288                                      const void *Decoder);
 289
 290 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 291                                uint64_t Address,
 292                                const void *Decoder);
 293
 294 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 295                                uint64_t Address,
 296                                const void *Decoder);
 297
 298 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 299                                uint64_t Address,
 300                                const void *Decoder);
 301
 302 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
 303                                uint64_t Address,
 304                                const void *Decoder);
 305
 306 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 307                                        unsigned Insn,
 308                                        uint64_t Address,
 309                                        const void *Decoder);
 310
 311 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
 312                                        unsigned Value,
 313                                        uint64_t Address,
 314                                        const void *Decoder);
 315
 316 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
 317                                     unsigned Value,
 318                                     uint64_t Address,
 319                                     const void *Decoder);
 320
 321 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
 322                                   unsigned Value,
 323                                   uint64_t Address,
 324                                   const void *Decoder);
 325
 326 static DecodeStatus DecodeSimm4(MCInst &Inst,
 327                                 unsigned Value,
 328                                 uint64_t Address,
 329                                 const void *Decoder);
 330
 331 static DecodeStatus DecodeSimm16(MCInst &Inst,
 332                                  unsigned Insn,
 333                                  uint64_t Address,
 334                                  const void *Decoder);
 335
 336 // Decode the immediate field of an LSA instruction which
 337 // is off by one.
 338 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 339                                  unsigned Insn,
 340                                  uint64_t Address,
 341                                  const void *Decoder);
 342
 343 static DecodeStatus DecodeInsSize(MCInst &Inst,
 344                                   unsigned Insn,
 345                                   uint64_t Address,
 346                                   const void *Decoder);
 347
 348 static DecodeStatus DecodeExtSize(MCInst &Inst,
 349                                   unsigned Insn,
 350                                   uint64_t Address,
 351                                   const void *Decoder);
 352
 353 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 354                                      uint64_t Address, const void *Decoder);
 355
 356 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 357                                      uint64_t Address, const void *Decoder);
 358
 359 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
 360                                   uint64_t Address, const void *Decoder);
 361
 362 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
 363                                     uint64_t Address, const void *Decoder);
 364
 365 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
 366                                    uint64_t Address, const void *Decoder);
 367
 368 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
 369                                      uint64_t Address, const void *Decoder);
 370
 371 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 372 /// handle.
 373 template <typename InsnType>
 374 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 375                                    const void *Decoder);
 376
 377 template <typename InsnType>
 378 static DecodeStatus
 379 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 380                       const void *Decoder);
 381
 382 template <typename InsnType>
 383 static DecodeStatus
 384 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 385                        const void *Decoder);
 386
 387 template <typename InsnType>
 388 static DecodeStatus
 389 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 390                        const void *Decoder);
 391
 392 template <typename InsnType>
 393 static DecodeStatus
 394 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 395                        const void *Decoder);
 396
 397 template <typename InsnType>
 398 static DecodeStatus
 399 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 400                       const void *Decoder);
 401
 402 template <typename InsnType>
 403 static DecodeStatus
 404 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 405                        const void *Decoder);
 406
 407 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
 408                                          uint64_t Address,
 409                                          const void *Decoder);
 410
 411 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
 412                                            uint64_t Address,
 413                                            const void *Decoder);
 414
 415 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
 416                                        uint64_t Address,
 417                                        const void *Decoder);
 418
 419 namespace llvm {
 420 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 421               TheMips64elTarget;
 422 }
 423
 424 static MCDisassembler *createMipsDisassembler(
 425                        const Target &T,
 426                        const MCSubtargetInfo &STI,
 427                        MCContext &Ctx) {
 428   return new MipsDisassembler(STI, Ctx, true);
 429 }
 430
 431 static MCDisassembler *createMipselDisassembler(
 432                        const Target &T,
 433                        const MCSubtargetInfo &STI,
 434                        MCContext &Ctx) {
 435   return new MipsDisassembler(STI, Ctx, false);
 436 }
 437
 438 extern "C" void LLVMInitializeMipsDisassembler() {
 439   // Register the disassembler.
 440   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 441                                          createMipsDisassembler);
 442   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 443                                          createMipselDisassembler);
 444   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 445                                          createMipsDisassembler);
 446   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 447                                          createMipselDisassembler);
 448 }
 449
 450 #include "MipsGenDisassemblerTables.inc"
 451
 452 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 453   const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
 454   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 455   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 456 }
 457
 458 template <typename InsnType>
 459 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 460                                    const void *Decoder) {
 461   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 462   // The size of the n field depends on the element size
 463   // The register class also depends on this.
 464   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 465   unsigned NSize = 0;
 466   DecodeFN RegDecoder = nullptr;
 467   if ((tmp & 0x18) == 0x00) { // INSVE_B
 468     NSize = 4;
 469     RegDecoder = DecodeMSA128BRegisterClass;
 470   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 471     NSize = 3;
 472     RegDecoder = DecodeMSA128HRegisterClass;
 473   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 474     NSize = 2;
 475     RegDecoder = DecodeMSA128WRegisterClass;
 476   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 477     NSize = 1;
 478     RegDecoder = DecodeMSA128DRegisterClass;
 479   } else
 480     llvm_unreachable("Invalid encoding");
 481
 482   assert(NSize != 0 && RegDecoder != nullptr);
 483
 484   // $wd
 485   tmp = fieldFromInstruction(insn, 6, 5);
 486   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 487     return MCDisassembler::Fail;
 488   // $wd_in
 489   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 490     return MCDisassembler::Fail;
 491   // $n
 492   tmp = fieldFromInstruction(insn, 16, NSize);
 493   MI.addOperand(MCOperand::createImm(tmp));
 494   // $ws
 495   tmp = fieldFromInstruction(insn, 11, 5);
 496   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 497     return MCDisassembler::Fail;
 498   // $n2
 499   MI.addOperand(MCOperand::createImm(0));
 500
 501   return MCDisassembler::Success;
 502 }
 503
 504 template <typename InsnType>
 505 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 506                                           uint64_t Address,
 507                                           const void *Decoder) {
 508   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 509   // (otherwise we would have matched the ADDI instruction from the earlier
 510   // ISA's instead).
 511   //
 512   // We have:
 513   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 514   //      BOVC if rs >= rt
 515   //      BEQZALC if rs == 0 && rt != 0
 516   //      BEQC if rs < rt && rs != 0
 517
 518   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 519   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 520   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 521   bool HasRs = false;
 522
 523   if (Rs >= Rt) {
 524     MI.setOpcode(Mips::BOVC);
 525     HasRs = true;
 526   } else if (Rs != 0 && Rs < Rt) {
 527     MI.setOpcode(Mips::BEQC);
 528     HasRs = true;
 529   } else
 530     MI.setOpcode(Mips::BEQZALC);
 531
 532   if (HasRs)
 533     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 534                                        Rs)));
 535
 536   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 537                                      Rt)));
 538   MI.addOperand(MCOperand::createImm(Imm));
 539
 540   return MCDisassembler::Success;
 541 }
 542
 543 template <typename InsnType>
 544 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 545                                            uint64_t Address,
 546                                            const void *Decoder) {
 547   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 548   // (otherwise we would have matched the ADDI instruction from the earlier
 549   // ISA's instead).
 550   //
 551   // We have:
 552   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 553   //      BNVC if rs >= rt
 554   //      BNEZALC if rs == 0 && rt != 0
 555   //      BNEC if rs < rt && rs != 0
 556
 557   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 558   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 559   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 560   bool HasRs = false;
 561
 562   if (Rs >= Rt) {
 563     MI.setOpcode(Mips::BNVC);
 564     HasRs = true;
 565   } else if (Rs != 0 && Rs < Rt) {
 566     MI.setOpcode(Mips::BNEC);
 567     HasRs = true;
 568   } else
 569     MI.setOpcode(Mips::BNEZALC);
 570
 571   if (HasRs)
 572     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 573                                        Rs)));
 574
 575   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 576                                      Rt)));
 577   MI.addOperand(MCOperand::createImm(Imm));
 578
 579   return MCDisassembler::Success;
 580 }
 581
 582 template <typename InsnType>
 583 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 584                                            uint64_t Address,
 585                                            const void *Decoder) {
 586   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 587   // (otherwise we would have matched the BLEZL instruction from the earlier
 588   // ISA's instead).
 589   //
 590   // We have:
 591   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 592   //      Invalid if rs == 0
 593   //      BLEZC   if rs == 0  && rt != 0
 594   //      BGEZC   if rs == rt && rt != 0
 595   //      BGEC    if rs != rt && rs != 0  && rt != 0
 596
 597   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 598   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 599   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 600   bool HasRs = false;
 601
 602   if (Rt == 0)
 603     return MCDisassembler::Fail;
 604   else if (Rs == 0)
 605     MI.setOpcode(Mips::BLEZC);
 606   else if (Rs == Rt)
 607     MI.setOpcode(Mips::BGEZC);
 608   else {
 609     HasRs = true;
 610     MI.setOpcode(Mips::BGEC);
 611   }
 612
 613   if (HasRs)
 614     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 615                                        Rs)));
 616
 617   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 618                                      Rt)));
 619
 620   MI.addOperand(MCOperand::createImm(Imm));
 621
 622   return MCDisassembler::Success;
 623 }
 624
 625 template <typename InsnType>
 626 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 627                                            uint64_t Address,
 628                                            const void *Decoder) {
 629   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 630   // (otherwise we would have matched the BGTZL instruction from the earlier
 631   // ISA's instead).
 632   //
 633   // We have:
 634   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 635   //      Invalid if rs == 0
 636   //      BGTZC   if rs == 0  && rt != 0
 637   //      BLTZC   if rs == rt && rt != 0
 638   //      BLTC    if rs != rt && rs != 0  && rt != 0
 639
 640   bool HasRs = false;
 641
 642   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 643   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 644   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 645
 646   if (Rt == 0)
 647     return MCDisassembler::Fail;
 648   else if (Rs == 0)
 649     MI.setOpcode(Mips::BGTZC);
 650   else if (Rs == Rt)
 651     MI.setOpcode(Mips::BLTZC);
 652   else {
 653     MI.setOpcode(Mips::BLTC);
 654     HasRs = true;
 655   }
 656
 657   if (HasRs)
 658     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 659                                               Rs)));
 660
 661   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 662                                      Rt)));
 663
 664   MI.addOperand(MCOperand::createImm(Imm));
 665
 666   return MCDisassembler::Success;
 667 }
 668
 669 template <typename InsnType>
 670 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 671                                           uint64_t Address,
 672                                           const void *Decoder) {
 673   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 674   // (otherwise we would have matched the BGTZ instruction from the earlier
 675   // ISA's instead).
 676   //
 677   // We have:
 678   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 679   //      BGTZ    if rt == 0
 680   //      BGTZALC if rs == 0 && rt != 0
 681   //      BLTZALC if rs != 0 && rs == rt
 682   //      BLTUC   if rs != 0 && rs != rt
 683
 684   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 685   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 686   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 687   bool HasRs = false;
 688   bool HasRt = false;
 689
 690   if (Rt == 0) {
 691     MI.setOpcode(Mips::BGTZ);
 692     HasRs = true;
 693   } else if (Rs == 0) {
 694     MI.setOpcode(Mips::BGTZALC);
 695     HasRt = true;
 696   } else if (Rs == Rt) {
 697     MI.setOpcode(Mips::BLTZALC);
 698     HasRs = true;
 699   } else {
 700     MI.setOpcode(Mips::BLTUC);
 701     HasRs = true;
 702     HasRt = true;
 703   }
 704
 705   if (HasRs)
 706     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 707                                        Rs)));
 708
 709   if (HasRt)
 710     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 711                                        Rt)));
 712
 713   MI.addOperand(MCOperand::createImm(Imm));
 714
 715   return MCDisassembler::Success;
 716 }
 717
 718 template <typename InsnType>
 719 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 720                                            uint64_t Address,
 721                                            const void *Decoder) {
 722   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 723   // (otherwise we would have matched the BLEZL instruction from the earlier
 724   // ISA's instead).
 725   //
 726   // We have:
 727   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 728   //      Invalid   if rs == 0
 729   //      BLEZALC   if rs == 0  && rt != 0
 730   //      BGEZALC   if rs == rt && rt != 0
 731   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 732
 733   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 734   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 735   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 736   bool HasRs = false;
 737
 738   if (Rt == 0)
 739     return MCDisassembler::Fail;
 740   else if (Rs == 0)
 741     MI.setOpcode(Mips::BLEZALC);
 742   else if (Rs == Rt)
 743     MI.setOpcode(Mips::BGEZALC);
 744   else {
 745     HasRs = true;
 746     MI.setOpcode(Mips::BGEUC);
 747   }
 748
 749   if (HasRs)
 750     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 751                                        Rs)));
 752   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 753                                      Rt)));
 754
 755   MI.addOperand(MCOperand::createImm(Imm));
 756
 757   return MCDisassembler::Success;
 758 }
 759
 760 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
 761 /// according to the given endianess.
 762 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
 763                                       uint64_t &Size, uint32_t &Insn,
 764                                       bool IsBigEndian) {
 765   // We want to read exactly 2 Bytes of data.
 766   if (Bytes.size() < 2) {
 767     Size = 0;
 768     return MCDisassembler::Fail;
 769   }
 770
 771   if (IsBigEndian) {
 772     Insn = (Bytes[0] << 8) | Bytes[1];
 773   } else {
 774     Insn = (Bytes[1] << 8) | Bytes[0];
 775   }
 776
 777   return MCDisassembler::Success;
 778 }
 779
 780 /// Read four bytes from the ArrayRef and return 32 bit word sorted
 781 /// according to the given endianess
 782 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
 783                                       uint64_t &Size, uint32_t &Insn,
 784                                       bool IsBigEndian, bool IsMicroMips) {
 785   // We want to read exactly 4 Bytes of data.
 786   if (Bytes.size() < 4) {
 787     Size = 0;
 788     return MCDisassembler::Fail;
 789   }
 790
 791   // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
 792   // always precede the low 16 bits in the instruction stream (that is, they
 793   // are placed at lower addresses in the instruction stream).
 794   //
 795   // microMIPS byte ordering:
 796   //   Big-endian:    0 | 1 | 2 | 3
 797   //   Little-endian: 1 | 0 | 3 | 2
 798
 799   if (IsBigEndian) {
 800     // Encoded as a big-endian 32-bit word in the stream.
 801     Insn =
 802         (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
 803   } else {
 804     if (IsMicroMips) {
 805       Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
 806              (Bytes[1] << 24);
 807     } else {
 808       Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
 809              (Bytes[3] << 24);
 810     }
 811   }
 812
 813   return MCDisassembler::Success;
 814 }
 815
 816 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 817                                               ArrayRef<uint8_t> Bytes,
 818                                               uint64_t Address,
 819                                               raw_ostream &VStream,
 820                                               raw_ostream &CStream) const {
 821   uint32_t Insn;
 822   DecodeStatus Result;
 823
 824   if (IsMicroMips) {
 825     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
 826
 827     DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
 828     // Calling the auto-generated decoder function.
 829     Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
 830                                this, STI);
 831     if (Result != MCDisassembler::Fail) {
 832       Size = 2;
 833       return Result;
 834     }
 835
 836     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
 837     if (Result == MCDisassembler::Fail)
 838       return MCDisassembler::Fail;
 839
 840     if (hasMips32r6()) {
 841       DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
 842       // Calling the auto-generated decoder function.
 843       Result = decodeInstruction(DecoderTableMicroMips32r632, Instr, Insn, Address,
 844                                  this, STI);
 845     } else {
 846       DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
 847       // Calling the auto-generated decoder function.
 848       Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
 849                                  this, STI);
 850     }
 851     if (Result != MCDisassembler::Fail) {
 852       Size = 4;
 853       return Result;
 854     }
 855     return MCDisassembler::Fail;
 856   }
 857
 858   Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 859   if (Result == MCDisassembler::Fail)
 860     return MCDisassembler::Fail;
 861
 862   if (hasCOP3()) {
 863     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 864     Result =
 865         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
 866     if (Result != MCDisassembler::Fail) {
 867       Size = 4;
 868       return Result;
 869     }
 870   }
 871
 872   if (hasMips32r6() && isGP64()) {
 873     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 874     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
 875                                Address, this, STI);
 876     if (Result != MCDisassembler::Fail) {
 877       Size = 4;
 878       return Result;
 879     }
 880   }
 881
 882   if (hasMips32r6()) {
 883     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 884     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
 885                                Address, this, STI);
 886     if (Result != MCDisassembler::Fail) {
 887       Size = 4;
 888       return Result;
 889     }
 890   }
 891
 892   if (isGP64()) {
 893     DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
 894     Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
 895                                Address, this, STI);
 896     if (Result != MCDisassembler::Fail) {
 897       Size = 4;
 898       return Result;
 899     }
 900   }
 901
 902   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 903   // Calling the auto-generated decoder function.
 904   Result =
 905       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 906   if (Result != MCDisassembler::Fail) {
 907     Size = 4;
 908     return Result;
 909   }
 910
 911   return MCDisassembler::Fail;
 912 }
 913
 914 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 915                                                  unsigned RegNo,
 916                                                  uint64_t Address,
 917                                                  const void *Decoder) {
 918
 919   return MCDisassembler::Fail;
 920
 921 }
 922
 923 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 924                                              unsigned RegNo,
 925                                              uint64_t Address,
 926                                              const void *Decoder) {
 927
 928   if (RegNo > 31)
 929     return MCDisassembler::Fail;
 930
 931   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 932   Inst.addOperand(MCOperand::createReg(Reg));
 933   return MCDisassembler::Success;
 934 }
 935
 936 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 937                                                unsigned RegNo,
 938                                                uint64_t Address,
 939                                                const void *Decoder) {
 940   if (RegNo > 7)
 941     return MCDisassembler::Fail;
 942   unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
 943   Inst.addOperand(MCOperand::createReg(Reg));
 944   return MCDisassembler::Success;
 945 }
 946
 947 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
 948                                                    unsigned RegNo,
 949                                                    uint64_t Address,
 950                                                    const void *Decoder) {
 951   if (RegNo > 7)
 952     return MCDisassembler::Fail;
 953   unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
 954   Inst.addOperand(MCOperand::createReg(Reg));
 955   return MCDisassembler::Success;
 956 }
 957
 958 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
 959                                                     unsigned RegNo,
 960                                                     uint64_t Address,
 961                                                     const void *Decoder) {
 962   if (RegNo > 7)
 963     return MCDisassembler::Fail;
 964   unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
 965   Inst.addOperand(MCOperand::createReg(Reg));
 966   return MCDisassembler::Success;
 967 }
 968
 969 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 970                                              unsigned RegNo,
 971                                              uint64_t Address,
 972                                              const void *Decoder) {
 973   if (RegNo > 31)
 974     return MCDisassembler::Fail;
 975   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 976   Inst.addOperand(MCOperand::createReg(Reg));
 977   return MCDisassembler::Success;
 978 }
 979
 980 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 981                                            unsigned RegNo,
 982                                            uint64_t Address,
 983                                            const void *Decoder) {
 984   if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
 985     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 986
 987   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 988 }
 989
 990 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 991                                             unsigned RegNo,
 992                                             uint64_t Address,
 993                                             const void *Decoder) {
 994   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 995 }
 996
 997 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 998                                              unsigned RegNo,
 999                                              uint64_t Address,
1000                                              const void *Decoder) {
1001   if (RegNo > 31)
1002     return MCDisassembler::Fail;
1003
1004   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1005   Inst.addOperand(MCOperand::createReg(Reg));
1006   return MCDisassembler::Success;
1007 }
1008
1009 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1010                                              unsigned RegNo,
1011                                              uint64_t Address,
1012                                              const void *Decoder) {
1013   if (RegNo > 31)
1014     return MCDisassembler::Fail;
1015
1016   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1017   Inst.addOperand(MCOperand::createReg(Reg));
1018   return MCDisassembler::Success;
1019 }
1020
1021 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1022                                            unsigned RegNo,
1023                                            uint64_t Address,
1024                                            const void *Decoder) {
1025   if (RegNo > 31)
1026     return MCDisassembler::Fail;
1027   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1028   Inst.addOperand(MCOperand::createReg(Reg));
1029   return MCDisassembler::Success;
1030 }
1031
1032 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1033                                            unsigned RegNo,
1034                                            uint64_t Address,
1035                                            const void *Decoder) {
1036   if (RegNo > 7)
1037     return MCDisassembler::Fail;
1038   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1039   Inst.addOperand(MCOperand::createReg(Reg));
1040   return MCDisassembler::Success;
1041 }
1042
1043 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1044                                              uint64_t Address,
1045                                              const void *Decoder) {
1046   if (RegNo > 31)
1047     return MCDisassembler::Fail;
1048
1049   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1050   Inst.addOperand(MCOperand::createReg(Reg));
1051   return MCDisassembler::Success;
1052 }
1053
1054 static DecodeStatus DecodeMem(MCInst &Inst,
1055                               unsigned Insn,
1056                               uint64_t Address,
1057                               const void *Decoder) {
1058   int Offset = SignExtend32<16>(Insn & 0xffff);
1059   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1060   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1061
1062   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1063   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1064
1065   if(Inst.getOpcode() == Mips::SC ||
1066      Inst.getOpcode() == Mips::SCD){
1067     Inst.addOperand(MCOperand::createReg(Reg));
1068   }
1069
1070   Inst.addOperand(MCOperand::createReg(Reg));
1071   Inst.addOperand(MCOperand::createReg(Base));
1072   Inst.addOperand(MCOperand::createImm(Offset));
1073
1074   return MCDisassembler::Success;
1075 }
1076
1077 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1078                               unsigned Insn,
1079                               uint64_t Address,
1080                               const void *Decoder) {
1081   int Offset = SignExtend32<16>(Insn & 0xffff);
1082   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1083   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1084
1085   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1086
1087   Inst.addOperand(MCOperand::createReg(Base));
1088   Inst.addOperand(MCOperand::createImm(Offset));
1089   Inst.addOperand(MCOperand::createImm(Hint));
1090
1091   return MCDisassembler::Success;
1092 }
1093
1094 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1095                                     unsigned Insn,
1096                                     uint64_t Address,
1097                                     const void *Decoder) {
1098   int Offset = SignExtend32<12>(Insn & 0xfff);
1099   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1100   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1101
1102   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1103
1104   Inst.addOperand(MCOperand::createReg(Base));
1105   Inst.addOperand(MCOperand::createImm(Offset));
1106   Inst.addOperand(MCOperand::createImm(Hint));
1107
1108   return MCDisassembler::Success;
1109 }
1110
1111 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
1112                                     unsigned Insn,
1113                                     uint64_t Address,
1114                                     const void *Decoder) {
1115   int Offset = fieldFromInstruction(Insn, 7, 9);
1116   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1117   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1118
1119   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1120
1121   Inst.addOperand(MCOperand::createReg(Base));
1122   Inst.addOperand(MCOperand::createImm(Offset));
1123   Inst.addOperand(MCOperand::createImm(Hint));
1124
1125   return MCDisassembler::Success;
1126 }
1127
1128 static DecodeStatus DecodeSyncI(MCInst &Inst,
1129                               unsigned Insn,
1130                               uint64_t Address,
1131                               const void *Decoder) {
1132   int Offset = SignExtend32<16>(Insn & 0xffff);
1133   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1134
1135   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1136
1137   Inst.addOperand(MCOperand::createReg(Base));
1138   Inst.addOperand(MCOperand::createImm(Offset));
1139
1140   return MCDisassembler::Success;
1141 }
1142
1143 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1144                                     uint64_t Address, const void *Decoder) {
1145   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1146   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1147   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1148
1149   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1150   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1151
1152   Inst.addOperand(MCOperand::createReg(Reg));
1153   Inst.addOperand(MCOperand::createReg(Base));
1154
1155   // The immediate field of an LD/ST instruction is scaled which means it must
1156   // be multiplied (when decoding) by the size (in bytes) of the instructions'
1157   // data format.
1158   // .b - 1 byte
1159   // .h - 2 bytes
1160   // .w - 4 bytes
1161   // .d - 8 bytes
1162   switch(Inst.getOpcode())
1163   {
1164   default:
1165     assert (0 && "Unexpected instruction");
1166     return MCDisassembler::Fail;
1167     break;
1168   case Mips::LD_B:
1169   case Mips::ST_B:
1170     Inst.addOperand(MCOperand::createImm(Offset));
1171     break;
1172   case Mips::LD_H:
1173   case Mips::ST_H:
1174     Inst.addOperand(MCOperand::createImm(Offset * 2));
1175     break;
1176   case Mips::LD_W:
1177   case Mips::ST_W:
1178     Inst.addOperand(MCOperand::createImm(Offset * 4));
1179     break;
1180   case Mips::LD_D:
1181   case Mips::ST_D:
1182     Inst.addOperand(MCOperand::createImm(Offset * 8));
1183     break;
1184   }
1185
1186   return MCDisassembler::Success;
1187 }
1188
1189 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1190                                     unsigned Insn,
1191                                     uint64_t Address,
1192                                     const void *Decoder) {
1193   unsigned Offset = Insn & 0xf;
1194   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1195   unsigned Base = fieldFromInstruction(Insn, 4, 3);
1196
1197   switch (Inst.getOpcode()) {
1198     case Mips::LBU16_MM:
1199     case Mips::LHU16_MM:
1200     case Mips::LW16_MM:
1201       if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1202             == MCDisassembler::Fail)
1203         return MCDisassembler::Fail;
1204       break;
1205     case Mips::SB16_MM:
1206     case Mips::SH16_MM:
1207     case Mips::SW16_MM:
1208       if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1209             == MCDisassembler::Fail)
1210         return MCDisassembler::Fail;
1211       break;
1212   }
1213
1214   if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1215         == MCDisassembler::Fail)
1216     return MCDisassembler::Fail;
1217
1218   switch (Inst.getOpcode()) {
1219     case Mips::LBU16_MM:
1220       if (Offset == 0xf)
1221         Inst.addOperand(MCOperand::createImm(-1));
1222       else
1223         Inst.addOperand(MCOperand::createImm(Offset));
1224       break;
1225     case Mips::SB16_MM:
1226       Inst.addOperand(MCOperand::createImm(Offset));
1227       break;
1228     case Mips::LHU16_MM:
1229     case Mips::SH16_MM:
1230       Inst.addOperand(MCOperand::createImm(Offset << 1));
1231       break;
1232     case Mips::LW16_MM:
1233     case Mips::SW16_MM:
1234       Inst.addOperand(MCOperand::createImm(Offset << 2));
1235       break;
1236   }
1237
1238   return MCDisassembler::Success;
1239 }
1240
1241 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1242                                           unsigned Insn,
1243                                           uint64_t Address,
1244                                           const void *Decoder) {
1245   unsigned Offset = Insn & 0x1F;
1246   unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1247
1248   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1249
1250   Inst.addOperand(MCOperand::createReg(Reg));
1251   Inst.addOperand(MCOperand::createReg(Mips::SP));
1252   Inst.addOperand(MCOperand::createImm(Offset << 2));
1253
1254   return MCDisassembler::Success;
1255 }
1256
1257 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1258                                           unsigned Insn,
1259                                           uint64_t Address,
1260                                           const void *Decoder) {
1261   unsigned Offset = Insn & 0x7F;
1262   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1263
1264   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1265
1266   Inst.addOperand(MCOperand::createReg(Reg));
1267   Inst.addOperand(MCOperand::createReg(Mips::GP));
1268   Inst.addOperand(MCOperand::createImm(Offset << 2));
1269
1270   return MCDisassembler::Success;
1271 }
1272
1273 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
1274                                                unsigned Insn,
1275                                                uint64_t Address,
1276                                                const void *Decoder) {
1277   int Offset = SignExtend32<4>(Insn & 0xf);
1278
1279   if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1280       == MCDisassembler::Fail)
1281     return MCDisassembler::Fail;
1282
1283   Inst.addOperand(MCOperand::createReg(Mips::SP));
1284   Inst.addOperand(MCOperand::createImm(Offset << 2));
1285
1286   return MCDisassembler::Success;
1287 }
1288
1289 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1290                                      unsigned Insn,
1291                                      uint64_t Address,
1292                                      const void *Decoder) {
1293   int Offset = SignExtend32<12>(Insn & 0x0fff);
1294   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1295   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1296
1297   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1298   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1299
1300   switch (Inst.getOpcode()) {
1301   case Mips::SWM32_MM:
1302   case Mips::LWM32_MM:
1303     if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1304         == MCDisassembler::Fail)
1305       return MCDisassembler::Fail;
1306     Inst.addOperand(MCOperand::createReg(Base));
1307     Inst.addOperand(MCOperand::createImm(Offset));
1308     break;
1309   case Mips::SC_MM:
1310     Inst.addOperand(MCOperand::createReg(Reg));
1311     // fallthrough
1312   default:
1313     Inst.addOperand(MCOperand::createReg(Reg));
1314     if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1315       Inst.addOperand(MCOperand::createReg(Reg+1));
1316
1317     Inst.addOperand(MCOperand::createReg(Base));
1318     Inst.addOperand(MCOperand::createImm(Offset));
1319   }
1320
1321   return MCDisassembler::Success;
1322 }
1323
1324 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1325                                      unsigned Insn,
1326                                      uint64_t Address,
1327                                      const void *Decoder) {
1328   int Offset = SignExtend32<16>(Insn & 0xffff);
1329   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1330   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1331
1332   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1333   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1334
1335   Inst.addOperand(MCOperand::createReg(Reg));
1336   Inst.addOperand(MCOperand::createReg(Base));
1337   Inst.addOperand(MCOperand::createImm(Offset));
1338
1339   return MCDisassembler::Success;
1340 }
1341
1342 static DecodeStatus DecodeFMem(MCInst &Inst,
1343                                unsigned Insn,
1344                                uint64_t Address,
1345                                const void *Decoder) {
1346   int Offset = SignExtend32<16>(Insn & 0xffff);
1347   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1348   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1349
1350   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1351   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1352
1353   Inst.addOperand(MCOperand::createReg(Reg));
1354   Inst.addOperand(MCOperand::createReg(Base));
1355   Inst.addOperand(MCOperand::createImm(Offset));
1356
1357   return MCDisassembler::Success;
1358 }
1359
1360 static DecodeStatus DecodeFMem2(MCInst &Inst,
1361                                unsigned Insn,
1362                                uint64_t Address,
1363                                const void *Decoder) {
1364   int Offset = SignExtend32<16>(Insn & 0xffff);
1365   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1366   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1367
1368   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1369   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1370
1371   Inst.addOperand(MCOperand::createReg(Reg));
1372   Inst.addOperand(MCOperand::createReg(Base));
1373   Inst.addOperand(MCOperand::createImm(Offset));
1374
1375   return MCDisassembler::Success;
1376 }
1377
1378 static DecodeStatus DecodeFMem3(MCInst &Inst,
1379                                unsigned Insn,
1380                                uint64_t Address,
1381                                const void *Decoder) {
1382   int Offset = SignExtend32<16>(Insn & 0xffff);
1383   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1384   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1385
1386   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1387   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1388
1389   Inst.addOperand(MCOperand::createReg(Reg));
1390   Inst.addOperand(MCOperand::createReg(Base));
1391   Inst.addOperand(MCOperand::createImm(Offset));
1392
1393   return MCDisassembler::Success;
1394 }
1395
1396 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1397                                     unsigned Insn,
1398                                     uint64_t Address,
1399                                     const void *Decoder) {
1400   int Offset = SignExtend32<11>(Insn & 0x07ff);
1401   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1402   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1403
1404   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1405   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1406
1407   Inst.addOperand(MCOperand::createReg(Reg));
1408   Inst.addOperand(MCOperand::createReg(Base));
1409   Inst.addOperand(MCOperand::createImm(Offset));
1410
1411   return MCDisassembler::Success;
1412 }
1413 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1414                                        unsigned Insn,
1415                                        uint64_t Address,
1416                                        const void *Decoder) {
1417   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1418   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1419   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1420
1421   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1422   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1423
1424   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1425     Inst.addOperand(MCOperand::createReg(Rt));
1426   }
1427
1428   Inst.addOperand(MCOperand::createReg(Rt));
1429   Inst.addOperand(MCOperand::createReg(Base));
1430   Inst.addOperand(MCOperand::createImm(Offset));
1431
1432   return MCDisassembler::Success;
1433 }
1434
1435 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1436                                               unsigned RegNo,
1437                                               uint64_t Address,
1438                                               const void *Decoder) {
1439   // Currently only hardware register 29 is supported.
1440   if (RegNo != 29)
1441     return  MCDisassembler::Fail;
1442   Inst.addOperand(MCOperand::createReg(Mips::HWR29));
1443   return MCDisassembler::Success;
1444 }
1445
1446 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1447                                               unsigned RegNo,
1448                                               uint64_t Address,
1449                                               const void *Decoder) {
1450   if (RegNo > 30 || RegNo %2)
1451     return MCDisassembler::Fail;
1452
1453   ;
1454   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1455   Inst.addOperand(MCOperand::createReg(Reg));
1456   return MCDisassembler::Success;
1457 }
1458
1459 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1460                                                 unsigned RegNo,
1461                                                 uint64_t Address,
1462                                                 const void *Decoder) {
1463   if (RegNo >= 4)
1464     return MCDisassembler::Fail;
1465
1466   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1467   Inst.addOperand(MCOperand::createReg(Reg));
1468   return MCDisassembler::Success;
1469 }
1470
1471 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1472                                                unsigned RegNo,
1473                                                uint64_t Address,
1474                                                const void *Decoder) {
1475   if (RegNo >= 4)
1476     return MCDisassembler::Fail;
1477
1478   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1479   Inst.addOperand(MCOperand::createReg(Reg));
1480   return MCDisassembler::Success;
1481 }
1482
1483 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1484                                                unsigned RegNo,
1485                                                uint64_t Address,
1486                                                const void *Decoder) {
1487   if (RegNo >= 4)
1488     return MCDisassembler::Fail;
1489
1490   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1491   Inst.addOperand(MCOperand::createReg(Reg));
1492   return MCDisassembler::Success;
1493 }
1494
1495 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1496                                                unsigned RegNo,
1497                                                uint64_t Address,
1498                                                const void *Decoder) {
1499   if (RegNo > 31)
1500     return MCDisassembler::Fail;
1501
1502   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1503   Inst.addOperand(MCOperand::createReg(Reg));
1504   return MCDisassembler::Success;
1505 }
1506
1507 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1508                                                unsigned RegNo,
1509                                                uint64_t Address,
1510                                                const void *Decoder) {
1511   if (RegNo > 31)
1512     return MCDisassembler::Fail;
1513
1514   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1515   Inst.addOperand(MCOperand::createReg(Reg));
1516   return MCDisassembler::Success;
1517 }
1518
1519 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1520                                                unsigned RegNo,
1521                                                uint64_t Address,
1522                                                const void *Decoder) {
1523   if (RegNo > 31)
1524     return MCDisassembler::Fail;
1525
1526   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1527   Inst.addOperand(MCOperand::createReg(Reg));
1528   return MCDisassembler::Success;
1529 }
1530
1531 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1532                                                unsigned RegNo,
1533                                                uint64_t Address,
1534                                                const void *Decoder) {
1535   if (RegNo > 31)
1536     return MCDisassembler::Fail;
1537
1538   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1539   Inst.addOperand(MCOperand::createReg(Reg));
1540   return MCDisassembler::Success;
1541 }
1542
1543 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1544                                                unsigned RegNo,
1545                                                uint64_t Address,
1546                                                const void *Decoder) {
1547   if (RegNo > 7)
1548     return MCDisassembler::Fail;
1549
1550   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1551   Inst.addOperand(MCOperand::createReg(Reg));
1552   return MCDisassembler::Success;
1553 }
1554
1555 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1556                                             unsigned RegNo,
1557                                             uint64_t Address,
1558                                             const void *Decoder) {
1559   if (RegNo > 31)
1560     return MCDisassembler::Fail;
1561
1562   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1563   Inst.addOperand(MCOperand::createReg(Reg));
1564   return MCDisassembler::Success;
1565 }
1566
1567 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1568                                        unsigned Offset,
1569                                        uint64_t Address,
1570                                        const void *Decoder) {
1571   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1572   Inst.addOperand(MCOperand::createImm(BranchOffset));
1573   return MCDisassembler::Success;
1574 }
1575
1576 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1577                                      unsigned Insn,
1578                                      uint64_t Address,
1579                                      const void *Decoder) {
1580
1581   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1582   Inst.addOperand(MCOperand::createImm(JumpOffset));
1583   return MCDisassembler::Success;
1584 }
1585
1586 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1587                                          unsigned Offset,
1588                                          uint64_t Address,
1589                                          const void *Decoder) {
1590   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1591
1592   Inst.addOperand(MCOperand::createImm(BranchOffset));
1593   return MCDisassembler::Success;
1594 }
1595
1596 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1597                                          unsigned Offset,
1598                                          uint64_t Address,
1599                                          const void *Decoder) {
1600   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1601
1602   Inst.addOperand(MCOperand::createImm(BranchOffset));
1603   return MCDisassembler::Success;
1604 }
1605
1606 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1607                                           unsigned Offset,
1608                                           uint64_t Address,
1609                                           const void *Decoder) {
1610   int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1611   Inst.addOperand(MCOperand::createImm(BranchOffset));
1612   return MCDisassembler::Success;
1613 }
1614
1615 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1616                                            unsigned Offset,
1617                                            uint64_t Address,
1618                                            const void *Decoder) {
1619   int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1620   Inst.addOperand(MCOperand::createImm(BranchOffset));
1621   return MCDisassembler::Success;
1622 }
1623
1624 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1625                                          unsigned Offset,
1626                                          uint64_t Address,
1627                                          const void *Decoder) {
1628   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1629   Inst.addOperand(MCOperand::createImm(BranchOffset));
1630   return MCDisassembler::Success;
1631 }
1632
1633 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1634                                        unsigned Insn,
1635                                        uint64_t Address,
1636                                        const void *Decoder) {
1637   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1638   Inst.addOperand(MCOperand::createImm(JumpOffset));
1639   return MCDisassembler::Success;
1640 }
1641
1642 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1643                                        unsigned Value,
1644                                        uint64_t Address,
1645                                        const void *Decoder) {
1646   if (Value == 0)
1647     Inst.addOperand(MCOperand::createImm(1));
1648   else if (Value == 0x7)
1649     Inst.addOperand(MCOperand::createImm(-1));
1650   else
1651     Inst.addOperand(MCOperand::createImm(Value << 2));
1652   return MCDisassembler::Success;
1653 }
1654
1655 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1656                                     unsigned Value,
1657                                     uint64_t Address,
1658                                     const void *Decoder) {
1659   Inst.addOperand(MCOperand::createImm(Value << 2));
1660   return MCDisassembler::Success;
1661 }
1662
1663 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1664                                   unsigned Value,
1665                                   uint64_t Address,
1666                                   const void *Decoder) {
1667   if (Value == 0x7F)
1668     Inst.addOperand(MCOperand::createImm(-1));
1669   else
1670     Inst.addOperand(MCOperand::createImm(Value));
1671   return MCDisassembler::Success;
1672 }
1673
1674 static DecodeStatus DecodeSimm4(MCInst &Inst,
1675                                 unsigned Value,
1676                                 uint64_t Address,
1677                                 const void *Decoder) {
1678   Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value)));
1679   return MCDisassembler::Success;
1680 }
1681
1682 static DecodeStatus DecodeSimm16(MCInst &Inst,
1683                                  unsigned Insn,
1684                                  uint64_t Address,
1685                                  const void *Decoder) {
1686   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn)));
1687   return MCDisassembler::Success;
1688 }
1689
1690 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1691                                  unsigned Insn,
1692                                  uint64_t Address,
1693                                  const void *Decoder) {
1694   // We add one to the immediate field as it was encoded as 'imm - 1'.
1695   Inst.addOperand(MCOperand::createImm(Insn + 1));
1696   return MCDisassembler::Success;
1697 }
1698
1699 static DecodeStatus DecodeInsSize(MCInst &Inst,
1700                                   unsigned Insn,
1701                                   uint64_t Address,
1702                                   const void *Decoder) {
1703   // First we need to grab the pos(lsb) from MCInst.
1704   int Pos = Inst.getOperand(2).getImm();
1705   int Size = (int) Insn - Pos + 1;
1706   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1707   return MCDisassembler::Success;
1708 }
1709
1710 static DecodeStatus DecodeExtSize(MCInst &Inst,
1711                                   unsigned Insn,
1712                                   uint64_t Address,
1713                                   const void *Decoder) {
1714   int Size = (int) Insn  + 1;
1715   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1716   return MCDisassembler::Success;
1717 }
1718
1719 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1720                                      uint64_t Address, const void *Decoder) {
1721   Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
1722   return MCDisassembler::Success;
1723 }
1724
1725 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1726                                      uint64_t Address, const void *Decoder) {
1727   Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
1728   return MCDisassembler::Success;
1729 }
1730
1731 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1732                                   uint64_t Address, const void *Decoder) {
1733   int32_t DecodedValue;
1734   switch (Insn) {
1735   case 0: DecodedValue = 256; break;
1736   case 1: DecodedValue = 257; break;
1737   case 510: DecodedValue = -258; break;
1738   case 511: DecodedValue = -257; break;
1739   default: DecodedValue = SignExtend32<9>(Insn); break;
1740   }
1741   Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
1742   return MCDisassembler::Success;
1743 }
1744
1745 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1746                                     uint64_t Address, const void *Decoder) {
1747   // Insn must be >= 0, since it is unsigned that condition is always true.
1748   assert(Insn < 16);
1749   int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1750                              255, 32768, 65535};
1751   Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
1752   return MCDisassembler::Success;
1753 }
1754
1755 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1756                                     uint64_t Address, const void *Decoder) {
1757   Inst.addOperand(MCOperand::createImm(Insn << 2));
1758   return MCDisassembler::Success;
1759 }
1760
1761 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1762                                          unsigned Insn,
1763                                          uint64_t Address,
1764                                          const void *Decoder) {
1765   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1766                      Mips::S6, Mips::FP};
1767   unsigned RegNum;
1768
1769   unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1770   // Empty register lists are not allowed.
1771   if (RegLst == 0)
1772     return MCDisassembler::Fail;
1773
1774   RegNum = RegLst & 0xf;
1775   for (unsigned i = 0; i < RegNum; i++)
1776     Inst.addOperand(MCOperand::createReg(Regs[i]));
1777
1778   if (RegLst & 0x10)
1779     Inst.addOperand(MCOperand::createReg(Mips::RA));
1780
1781   return MCDisassembler::Success;
1782 }
1783
1784 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1785                                            uint64_t Address,
1786                                            const void *Decoder) {
1787   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1788   unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1789   unsigned RegNum = RegLst & 0x3;
1790
1791   for (unsigned i = 0; i <= RegNum; i++)
1792     Inst.addOperand(MCOperand::createReg(Regs[i]));
1793
1794   Inst.addOperand(MCOperand::createReg(Mips::RA));
1795
1796   return MCDisassembler::Success;
1797 }
1798
1799 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
1800                                        uint64_t Address, const void *Decoder) {
1801
1802   unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
1803
1804   switch (RegPair) {
1805   default:
1806     return MCDisassembler::Fail;
1807   case 0:
1808     Inst.addOperand(MCOperand::createReg(Mips::A1));
1809     Inst.addOperand(MCOperand::createReg(Mips::A2));
1810     break;
1811   case 1:
1812     Inst.addOperand(MCOperand::createReg(Mips::A1));
1813     Inst.addOperand(MCOperand::createReg(Mips::A3));
1814     break;
1815   case 2:
1816     Inst.addOperand(MCOperand::createReg(Mips::A2));
1817     Inst.addOperand(MCOperand::createReg(Mips::A3));
1818     break;
1819   case 3:
1820     Inst.addOperand(MCOperand::createReg(Mips::A0));
1821     Inst.addOperand(MCOperand::createReg(Mips::S5));
1822     break;
1823   case 4:
1824     Inst.addOperand(MCOperand::createReg(Mips::A0));
1825     Inst.addOperand(MCOperand::createReg(Mips::S6));
1826     break;
1827   case 5:
1828     Inst.addOperand(MCOperand::createReg(Mips::A0));
1829     Inst.addOperand(MCOperand::createReg(Mips::A1));
1830     break;
1831   case 6:
1832     Inst.addOperand(MCOperand::createReg(Mips::A0));
1833     Inst.addOperand(MCOperand::createReg(Mips::A2));
1834     break;
1835   case 7:
1836     Inst.addOperand(MCOperand::createReg(Mips::A0));
1837     Inst.addOperand(MCOperand::createReg(Mips::A3));
1838     break;
1839   }
1840
1841   return MCDisassembler::Success;
1842 }
1843
1844 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1845                                      uint64_t Address, const void *Decoder) {
1846   Inst.addOperand(MCOperand::createImm(SignExtend32<23>(Insn) << 2));
1847   return MCDisassembler::Success;
1848 }