1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Mips Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCDisassembler.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/MathExtras.h"
22 #include "llvm/Support/MemoryObject.h"
23 #include "llvm/Support/TargetRegistry.h"
27 typedef MCDisassembler::DecodeStatus DecodeStatus;
31 /// MipsDisassemblerBase - a disasembler class for Mips.
32 class MipsDisassemblerBase : public MCDisassembler {
34 /// Constructor - Initializes the disassembler.
36 MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
38 MCDisassembler(STI), RegInfo(Info),
39 IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
41 virtual ~MipsDisassemblerBase() {}
43 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
45 bool isN64() const { return IsN64; }
48 OwningPtr<const MCRegisterInfo> RegInfo;
54 /// MipsDisassembler - a disasembler class for Mips32.
55 class MipsDisassembler : public MipsDisassemblerBase {
58 /// Constructor - Initializes the disassembler.
60 MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
62 MipsDisassemblerBase(STI, Info, bigEndian) {
63 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
66 /// getInstruction - See MCDisassembler.
67 virtual DecodeStatus getInstruction(MCInst &instr,
69 const MemoryObject ®ion,
72 raw_ostream &cStream) const;
76 /// Mips64Disassembler - a disasembler class for Mips64.
77 class Mips64Disassembler : public MipsDisassemblerBase {
79 /// Constructor - Initializes the disassembler.
81 Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
83 MipsDisassemblerBase(STI, Info, bigEndian) {}
85 /// getInstruction - See MCDisassembler.
86 virtual DecodeStatus getInstruction(MCInst &instr,
88 const MemoryObject ®ion,
91 raw_ostream &cStream) const;
94 } // end anonymous namespace
96 // Forward declare these because the autogenerated code will reference them.
97 // Definitions are further down.
98 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
101 const void *Decoder);
103 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
106 const void *Decoder);
108 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
111 const void *Decoder);
113 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
116 const void *Decoder);
118 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
121 const void *Decoder);
123 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
126 const void *Decoder);
128 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
131 const void *Decoder);
133 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
136 const void *Decoder);
138 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
141 const void *Decoder);
143 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
146 const void *Decoder);
148 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
151 const void *Decoder);
153 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
156 const void *Decoder);
158 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
161 const void *Decoder);
163 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
166 const void *Decoder);
168 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
171 const void *Decoder);
173 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
176 const void *Decoder);
178 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
181 const void *Decoder);
183 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
186 const void *Decoder);
188 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
191 const void *Decoder);
193 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
196 const void *Decoder);
198 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
201 const void *Decoder);
203 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
206 const void *Decoder);
208 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
209 // shifted left by 1 bit.
210 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
213 const void *Decoder);
215 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
216 // shifted left by 1 bit.
217 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
220 const void *Decoder);
222 static DecodeStatus DecodeMem(MCInst &Inst,
225 const void *Decoder);
227 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
228 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
233 const void *Decoder);
235 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
238 const void *Decoder);
240 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
242 const void *Decoder);
244 static DecodeStatus DecodeSimm16(MCInst &Inst,
247 const void *Decoder);
249 // Decode the immediate field of an LSA instruction which
251 static DecodeStatus DecodeLSAImm(MCInst &Inst,
254 const void *Decoder);
256 static DecodeStatus DecodeInsSize(MCInst &Inst,
259 const void *Decoder);
261 static DecodeStatus DecodeExtSize(MCInst &Inst,
264 const void *Decoder);
266 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
268 template <typename InsnType>
269 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
270 const void *Decoder);
272 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
276 static MCDisassembler *createMipsDisassembler(
278 const MCSubtargetInfo &STI) {
279 return new MipsDisassembler(STI, T.createMCRegInfo(""), true);
282 static MCDisassembler *createMipselDisassembler(
284 const MCSubtargetInfo &STI) {
285 return new MipsDisassembler(STI, T.createMCRegInfo(""), false);
288 static MCDisassembler *createMips64Disassembler(
290 const MCSubtargetInfo &STI) {
291 return new Mips64Disassembler(STI, T.createMCRegInfo(""), true);
294 static MCDisassembler *createMips64elDisassembler(
296 const MCSubtargetInfo &STI) {
297 return new Mips64Disassembler(STI, T.createMCRegInfo(""), false);
300 extern "C" void LLVMInitializeMipsDisassembler() {
301 // Register the disassembler.
302 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
303 createMipsDisassembler);
304 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
305 createMipselDisassembler);
306 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
307 createMips64Disassembler);
308 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
309 createMips64elDisassembler);
312 #include "MipsGenDisassemblerTables.inc"
314 template <typename InsnType>
315 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
316 const void *Decoder) {
317 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
318 // The size of the n field depends on the element size
319 // The register class also depends on this.
320 InsnType tmp = fieldFromInstruction(insn, 17, 5);
322 DecodeFN RegDecoder = nullptr;
323 if ((tmp & 0x18) == 0x00) { // INSVE_B
325 RegDecoder = DecodeMSA128BRegisterClass;
326 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
328 RegDecoder = DecodeMSA128HRegisterClass;
329 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
331 RegDecoder = DecodeMSA128WRegisterClass;
332 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
334 RegDecoder = DecodeMSA128DRegisterClass;
336 llvm_unreachable("Invalid encoding");
338 assert(NSize != 0 && RegDecoder != nullptr);
341 tmp = fieldFromInstruction(insn, 6, 5);
342 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
343 return MCDisassembler::Fail;
345 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
346 return MCDisassembler::Fail;
348 tmp = fieldFromInstruction(insn, 16, NSize);
349 MI.addOperand(MCOperand::CreateImm(tmp));
351 tmp = fieldFromInstruction(insn, 11, 5);
352 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
353 return MCDisassembler::Fail;
355 MI.addOperand(MCOperand::CreateImm(0));
357 return MCDisassembler::Success;
360 /// readInstruction - read four bytes from the MemoryObject
361 /// and return 32 bit word sorted according to the given endianess
362 static DecodeStatus readInstruction32(const MemoryObject ®ion,
370 // We want to read exactly 4 Bytes of data.
371 if (region.readBytes(address, 4, Bytes) == -1) {
373 return MCDisassembler::Fail;
377 // Encoded as a big-endian 32-bit word in the stream.
378 insn = (Bytes[3] << 0) |
384 // Encoded as a small-endian 32-bit word in the stream.
385 // Little-endian byte ordering:
386 // mips32r2: 4 | 3 | 2 | 1
387 // microMIPS: 2 | 1 | 4 | 3
389 insn = (Bytes[2] << 0) |
394 insn = (Bytes[0] << 0) |
401 return MCDisassembler::Success;
405 MipsDisassembler::getInstruction(MCInst &instr,
407 const MemoryObject &Region,
409 raw_ostream &vStream,
410 raw_ostream &cStream) const {
413 DecodeStatus Result = readInstruction32(Region, Address, Size,
414 Insn, isBigEndian, IsMicroMips);
415 if (Result == MCDisassembler::Fail)
416 return MCDisassembler::Fail;
419 // Calling the auto-generated decoder function.
420 Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
422 if (Result != MCDisassembler::Fail) {
426 return MCDisassembler::Fail;
429 // Calling the auto-generated decoder function.
430 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
432 if (Result != MCDisassembler::Fail) {
437 return MCDisassembler::Fail;
441 Mips64Disassembler::getInstruction(MCInst &instr,
443 const MemoryObject &Region,
445 raw_ostream &vStream,
446 raw_ostream &cStream) const {
449 DecodeStatus Result = readInstruction32(Region, Address, Size,
450 Insn, isBigEndian, false);
451 if (Result == MCDisassembler::Fail)
452 return MCDisassembler::Fail;
454 // Calling the auto-generated decoder function.
455 Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
457 if (Result != MCDisassembler::Fail) {
461 // If we fail to decode in Mips64 decoder space we can try in Mips32
462 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
464 if (Result != MCDisassembler::Fail) {
469 return MCDisassembler::Fail;
472 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
473 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
474 return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
477 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
480 const void *Decoder) {
482 return MCDisassembler::Fail;
486 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
489 const void *Decoder) {
492 return MCDisassembler::Fail;
494 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
495 Inst.addOperand(MCOperand::CreateReg(Reg));
496 return MCDisassembler::Success;
499 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
502 const void *Decoder) {
504 return MCDisassembler::Fail;
505 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
506 Inst.addOperand(MCOperand::CreateReg(Reg));
507 return MCDisassembler::Success;
510 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
513 const void *Decoder) {
514 if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
515 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
517 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
520 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
523 const void *Decoder) {
524 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
527 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
530 const void *Decoder) {
532 return MCDisassembler::Fail;
534 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
535 Inst.addOperand(MCOperand::CreateReg(Reg));
536 return MCDisassembler::Success;
539 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
542 const void *Decoder) {
544 return MCDisassembler::Fail;
546 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
547 Inst.addOperand(MCOperand::CreateReg(Reg));
548 return MCDisassembler::Success;
551 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
554 const void *Decoder) {
556 return MCDisassembler::Fail;
558 unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
559 Inst.addOperand(MCOperand::CreateReg(Reg));
560 return MCDisassembler::Success;
563 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
566 const void *Decoder) {
568 return MCDisassembler::Fail;
569 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
570 Inst.addOperand(MCOperand::CreateReg(Reg));
571 return MCDisassembler::Success;
574 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
577 const void *Decoder) {
579 return MCDisassembler::Fail;
580 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
581 Inst.addOperand(MCOperand::CreateReg(Reg));
582 return MCDisassembler::Success;
585 static DecodeStatus DecodeMem(MCInst &Inst,
588 const void *Decoder) {
589 int Offset = SignExtend32<16>(Insn & 0xffff);
590 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
591 unsigned Base = fieldFromInstruction(Insn, 21, 5);
593 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
594 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
596 if(Inst.getOpcode() == Mips::SC){
597 Inst.addOperand(MCOperand::CreateReg(Reg));
600 Inst.addOperand(MCOperand::CreateReg(Reg));
601 Inst.addOperand(MCOperand::CreateReg(Base));
602 Inst.addOperand(MCOperand::CreateImm(Offset));
604 return MCDisassembler::Success;
607 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
608 uint64_t Address, const void *Decoder) {
609 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
610 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
611 unsigned Base = fieldFromInstruction(Insn, 11, 5);
613 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
614 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
616 Inst.addOperand(MCOperand::CreateReg(Reg));
617 Inst.addOperand(MCOperand::CreateReg(Base));
619 // The immediate field of an LD/ST instruction is scaled which means it must
620 // be multiplied (when decoding) by the size (in bytes) of the instructions'
626 switch(Inst.getOpcode())
629 assert (0 && "Unexpected instruction");
630 return MCDisassembler::Fail;
634 Inst.addOperand(MCOperand::CreateImm(Offset));
638 Inst.addOperand(MCOperand::CreateImm(Offset << 1));
642 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
646 Inst.addOperand(MCOperand::CreateImm(Offset << 3));
650 return MCDisassembler::Success;
653 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
656 const void *Decoder) {
657 int Offset = SignExtend32<12>(Insn & 0x0fff);
658 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
659 unsigned Base = fieldFromInstruction(Insn, 16, 5);
661 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
662 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
664 if (Inst.getOpcode() == Mips::SC_MM)
665 Inst.addOperand(MCOperand::CreateReg(Reg));
667 Inst.addOperand(MCOperand::CreateReg(Reg));
668 Inst.addOperand(MCOperand::CreateReg(Base));
669 Inst.addOperand(MCOperand::CreateImm(Offset));
671 return MCDisassembler::Success;
674 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
677 const void *Decoder) {
678 int Offset = SignExtend32<16>(Insn & 0xffff);
679 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
680 unsigned Base = fieldFromInstruction(Insn, 16, 5);
682 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
683 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
685 Inst.addOperand(MCOperand::CreateReg(Reg));
686 Inst.addOperand(MCOperand::CreateReg(Base));
687 Inst.addOperand(MCOperand::CreateImm(Offset));
689 return MCDisassembler::Success;
692 static DecodeStatus DecodeFMem(MCInst &Inst,
695 const void *Decoder) {
696 int Offset = SignExtend32<16>(Insn & 0xffff);
697 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
698 unsigned Base = fieldFromInstruction(Insn, 21, 5);
700 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
701 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
703 Inst.addOperand(MCOperand::CreateReg(Reg));
704 Inst.addOperand(MCOperand::CreateReg(Base));
705 Inst.addOperand(MCOperand::CreateImm(Offset));
707 return MCDisassembler::Success;
711 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
714 const void *Decoder) {
715 // Currently only hardware register 29 is supported.
717 return MCDisassembler::Fail;
718 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
719 return MCDisassembler::Success;
722 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
725 const void *Decoder) {
726 if (RegNo > 30 || RegNo %2)
727 return MCDisassembler::Fail;
730 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
731 Inst.addOperand(MCOperand::CreateReg(Reg));
732 return MCDisassembler::Success;
735 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
738 const void *Decoder) {
740 return MCDisassembler::Fail;
742 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
743 Inst.addOperand(MCOperand::CreateReg(Reg));
744 return MCDisassembler::Success;
747 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
750 const void *Decoder) {
752 return MCDisassembler::Fail;
754 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
755 Inst.addOperand(MCOperand::CreateReg(Reg));
756 return MCDisassembler::Success;
759 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
762 const void *Decoder) {
764 return MCDisassembler::Fail;
766 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
767 Inst.addOperand(MCOperand::CreateReg(Reg));
768 return MCDisassembler::Success;
771 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
774 const void *Decoder) {
776 return MCDisassembler::Fail;
778 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
779 Inst.addOperand(MCOperand::CreateReg(Reg));
780 return MCDisassembler::Success;
783 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
786 const void *Decoder) {
788 return MCDisassembler::Fail;
790 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
791 Inst.addOperand(MCOperand::CreateReg(Reg));
792 return MCDisassembler::Success;
795 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
798 const void *Decoder) {
800 return MCDisassembler::Fail;
802 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
803 Inst.addOperand(MCOperand::CreateReg(Reg));
804 return MCDisassembler::Success;
807 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
810 const void *Decoder) {
812 return MCDisassembler::Fail;
814 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
815 Inst.addOperand(MCOperand::CreateReg(Reg));
816 return MCDisassembler::Success;
819 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
822 const void *Decoder) {
824 return MCDisassembler::Fail;
826 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
827 Inst.addOperand(MCOperand::CreateReg(Reg));
828 return MCDisassembler::Success;
831 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
834 const void *Decoder) {
835 unsigned BranchOffset = Offset & 0xffff;
836 BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
837 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
838 return MCDisassembler::Success;
841 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
844 const void *Decoder) {
846 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
847 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
848 return MCDisassembler::Success;
851 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
854 const void *Decoder) {
855 unsigned BranchOffset = Offset & 0xffff;
856 BranchOffset = SignExtend32<18>(BranchOffset << 1);
857 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
858 return MCDisassembler::Success;
861 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
864 const void *Decoder) {
865 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
866 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
867 return MCDisassembler::Success;
870 static DecodeStatus DecodeSimm16(MCInst &Inst,
873 const void *Decoder) {
874 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
875 return MCDisassembler::Success;
878 static DecodeStatus DecodeLSAImm(MCInst &Inst,
881 const void *Decoder) {
882 // We add one to the immediate field as it was encoded as 'imm - 1'.
883 Inst.addOperand(MCOperand::CreateImm(Insn + 1));
884 return MCDisassembler::Success;
887 static DecodeStatus DecodeInsSize(MCInst &Inst,
890 const void *Decoder) {
891 // First we need to grab the pos(lsb) from MCInst.
892 int Pos = Inst.getOperand(2).getImm();
893 int Size = (int) Insn - Pos + 1;
894 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
895 return MCDisassembler::Success;
898 static DecodeStatus DecodeExtSize(MCInst &Inst,
901 const void *Decoder) {
902 int Size = (int) Insn + 1;
903 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
904 return MCDisassembler::Success;