1 //===-- MipsASMBackend.cpp - Mips Asm Backend ----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsAsmBackend and MipsELFObjectWriter classes.
12 //===----------------------------------------------------------------------===//
15 #include "MipsFixupKinds.h"
16 #include "MCTargetDesc/MipsMCTargetDesc.h"
17 #include "llvm/MC/MCAsmBackend.h"
18 #include "llvm/MC/MCAssembler.h"
19 #include "llvm/MC/MCDirectives.h"
20 #include "llvm/MC/MCELFObjectWriter.h"
21 #include "llvm/MC/MCFixupKindInfo.h"
22 #include "llvm/MC/MCObjectWriter.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
29 // Prepare value for the target space for it
30 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
32 // Add/subtract and shift
39 case Mips::fixup_Mips_LO16:
40 case Mips::fixup_Mips_GPOFF_HI:
41 case Mips::fixup_Mips_GPOFF_LO:
42 case Mips::fixup_Mips_GOT_PAGE:
43 case Mips::fixup_Mips_GOT_OFST:
44 case Mips::fixup_Mips_GOT_DISP:
46 case Mips::fixup_Mips_PC16:
47 // So far we are only using this type for branches.
48 // For branches we start 1 instruction after the branch
49 // so the displacement will be one instruction size less.
51 // The displacement is then divided by 4 to give us an 18 bit
55 case Mips::fixup_Mips_26:
56 // So far we are only using this type for jumps.
57 // The displacement is then divided by 4 to give us an 28 bit
61 case Mips::fixup_Mips_HI16:
62 case Mips::fixup_Mips_GOT_Local:
63 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1.
64 Value = ((Value + 0x8000) >> 16) & 0xffff;
66 case Mips::fixup_Mips_HIGHER:
67 // Get the 3rd 16-bits.
68 Value = ((Value + 0x80008000LL) >> 32) & 0xffff;
70 case Mips::fixup_Mips_HIGHEST:
71 // Get the 4th 16-bits.
72 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;
80 class MipsAsmBackend : public MCAsmBackend {
81 Triple::OSType OSType;
82 bool IsLittle; // Big or little endian
83 bool Is64Bit; // 32 or 64 bit words
86 MipsAsmBackend(const Target &T, Triple::OSType _OSType,
87 bool _isLittle, bool _is64Bit)
88 :MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {}
90 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
91 return createMipsELFObjectWriter(OS,
92 MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
95 /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
96 /// data fragment, at the offset specified by the fixup and following the
97 /// fixup kind as appropriate.
98 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
99 uint64_t Value) const {
100 MCFixupKind Kind = Fixup.getKind();
101 Value = adjustFixupValue((unsigned)Kind, Value);
104 return; // Doesn't change encoding.
106 // Where do we start in the object
107 unsigned Offset = Fixup.getOffset();
108 // Number of bytes we need to fixup
109 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
110 // Used to point to big endian bytes
113 switch ((unsigned)Kind) {
114 case Mips::fixup_Mips_16:
117 case Mips::fixup_Mips_64:
125 // Grab current value, if any, from bits.
128 for (unsigned i = 0; i != NumBytes; ++i) {
129 unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
130 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
133 uint64_t Mask = ((uint64_t)(-1) >>
134 (64 - getFixupKindInfo(Kind).TargetSize));
135 CurVal |= Value & Mask;
137 // Write out the fixed up bytes back to the code/data bits.
138 for (unsigned i = 0; i != NumBytes; ++i) {
139 unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
140 Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
144 unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; }
146 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
147 const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = {
148 // This table *must* be in same the order of fixup_* kinds in
151 // name offset bits flags
152 { "fixup_Mips_16", 0, 16, 0 },
153 { "fixup_Mips_32", 0, 32, 0 },
154 { "fixup_Mips_REL32", 0, 32, 0 },
155 { "fixup_Mips_26", 0, 26, 0 },
156 { "fixup_Mips_HI16", 0, 16, 0 },
157 { "fixup_Mips_LO16", 0, 16, 0 },
158 { "fixup_Mips_GPREL16", 0, 16, 0 },
159 { "fixup_Mips_LITERAL", 0, 16, 0 },
160 { "fixup_Mips_GOT_Global", 0, 16, 0 },
161 { "fixup_Mips_GOT_Local", 0, 16, 0 },
162 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
163 { "fixup_Mips_CALL16", 0, 16, 0 },
164 { "fixup_Mips_GPREL32", 0, 32, 0 },
165 { "fixup_Mips_SHIFT5", 6, 5, 0 },
166 { "fixup_Mips_SHIFT6", 6, 5, 0 },
167 { "fixup_Mips_64", 0, 64, 0 },
168 { "fixup_Mips_TLSGD", 0, 16, 0 },
169 { "fixup_Mips_GOTTPREL", 0, 16, 0 },
170 { "fixup_Mips_TPREL_HI", 0, 16, 0 },
171 { "fixup_Mips_TPREL_LO", 0, 16, 0 },
172 { "fixup_Mips_TLSLDM", 0, 16, 0 },
173 { "fixup_Mips_DTPREL_HI", 0, 16, 0 },
174 { "fixup_Mips_DTPREL_LO", 0, 16, 0 },
175 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
176 { "fixup_Mips_GPOFF_HI", 0, 16, 0 },
177 { "fixup_Mips_GPOFF_LO", 0, 16, 0 },
178 { "fixup_Mips_GOT_PAGE", 0, 16, 0 },
179 { "fixup_Mips_GOT_OFST", 0, 16, 0 },
180 { "fixup_Mips_GOT_DISP", 0, 16, 0 },
181 { "fixup_Mips_HIGHER", 0, 16, 0 },
182 { "fixup_Mips_HIGHEST", 0, 16, 0 }
185 if (Kind < FirstTargetFixupKind)
186 return MCAsmBackend::getFixupKindInfo(Kind);
188 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
190 return Infos[Kind - FirstTargetFixupKind];
193 /// @name Target Relaxation Interfaces
196 /// MayNeedRelaxation - Check whether the given instruction may need
199 /// \param Inst - The instruction to test.
200 bool mayNeedRelaxation(const MCInst &Inst) const {
204 /// fixupNeedsRelaxation - Target specific predicate for whether a given
205 /// fixup requires the associated instruction to be relaxed.
206 bool fixupNeedsRelaxation(const MCFixup &Fixup,
208 const MCInstFragment *DF,
209 const MCAsmLayout &Layout) const {
211 assert(0 && "RelaxInstruction() unimplemented");
215 /// RelaxInstruction - Relax the instruction in the given fragment
216 /// to the next wider instruction.
218 /// \param Inst - The instruction to relax, which may be the same
220 /// \parm Res [output] - On return, the relaxed instruction.
221 void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
226 /// WriteNopData - Write an (optimal) nop sequence of Count bytes
227 /// to the given output. If the target cannot generate such a sequence,
228 /// it should return an error.
230 /// \return - True on success.
231 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
232 // Check for a less than instruction size number of bytes
233 // FIXME: 16 bit instructions are not handled yet here.
234 // We shouldn't be using a hard coded number for instruction size.
235 if (Count % 4) return false;
237 uint64_t NumNops = Count / 4;
238 for (uint64_t i = 0; i != NumNops; ++i)
242 }; // class MipsAsmBackend
247 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, StringRef TT) {
248 return new MipsAsmBackend(T, Triple(TT).getOS(),
249 /*IsLittle*/true, /*Is64Bit*/false);
252 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, StringRef TT) {
253 return new MipsAsmBackend(T, Triple(TT).getOS(),
254 /*IsLittle*/false, /*Is64Bit*/false);
257 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, StringRef TT) {
258 return new MipsAsmBackend(T, Triple(TT).getOS(),
259 /*IsLittle*/true, /*Is64Bit*/true);
262 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, StringRef TT) {
263 return new MipsAsmBackend(T, Triple(TT).getOS(),
264 /*IsLittle*/false, /*Is64Bit*/true);