1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsAsmBackend class.
12 //===----------------------------------------------------------------------===//
15 #include "MCTargetDesc/MipsFixupKinds.h"
16 #include "MCTargetDesc/MipsAsmBackend.h"
17 #include "MCTargetDesc/MipsMCTargetDesc.h"
18 #include "llvm/MC/MCAsmBackend.h"
19 #include "llvm/MC/MCAssembler.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCDirectives.h"
22 #include "llvm/MC/MCELFObjectWriter.h"
23 #include "llvm/MC/MCFixupKindInfo.h"
24 #include "llvm/MC/MCObjectWriter.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
32 // Prepare value for the target space for it
33 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
34 MCContext *Ctx = nullptr) {
36 unsigned Kind = Fixup.getKind();
38 // Add/subtract and shift
46 case Mips::fixup_Mips_LO16:
47 case Mips::fixup_Mips_GPREL16:
48 case Mips::fixup_Mips_GPOFF_HI:
49 case Mips::fixup_Mips_GPOFF_LO:
50 case Mips::fixup_Mips_GOT_PAGE:
51 case Mips::fixup_Mips_GOT_OFST:
52 case Mips::fixup_Mips_GOT_DISP:
53 case Mips::fixup_Mips_GOT_LO16:
54 case Mips::fixup_Mips_CALL_LO16:
55 case Mips::fixup_MICROMIPS_LO16:
56 case Mips::fixup_MICROMIPS_GOT_PAGE:
57 case Mips::fixup_MICROMIPS_GOT_OFST:
58 case Mips::fixup_MICROMIPS_GOT_DISP:
59 case Mips::fixup_MIPS_PCLO16:
61 case Mips::fixup_Mips_PC16:
62 // So far we are only using this type for branches.
63 // For branches we start 1 instruction after the branch
64 // so the displacement will be one instruction size less.
66 // The displacement is then divided by 4 to give us an 18 bit
67 // address range. Forcing a signed division because Value can be negative.
68 Value = (int64_t)Value / 4;
69 // We now check if Value can be encoded as a 16-bit signed immediate.
70 if (!isIntN(16, Value) && Ctx)
71 Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup");
73 case Mips::fixup_Mips_26:
74 // So far we are only using this type for jumps.
75 // The displacement is then divided by 4 to give us an 28 bit
79 case Mips::fixup_Mips_HI16:
80 case Mips::fixup_Mips_GOT_Local:
81 case Mips::fixup_Mips_GOT_HI16:
82 case Mips::fixup_Mips_CALL_HI16:
83 case Mips::fixup_MICROMIPS_HI16:
84 case Mips::fixup_MIPS_PCHI16:
85 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1.
86 Value = ((Value + 0x8000) >> 16) & 0xffff;
88 case Mips::fixup_Mips_HIGHER:
89 // Get the 3rd 16-bits.
90 Value = ((Value + 0x80008000LL) >> 32) & 0xffff;
92 case Mips::fixup_Mips_HIGHEST:
93 // Get the 4th 16-bits.
94 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;
96 case Mips::fixup_MICROMIPS_26_S1:
99 case Mips::fixup_MICROMIPS_PC16_S1:
101 // Forcing a signed division because Value can be negative.
102 Value = (int64_t)Value / 2;
103 // We now check if Value can be encoded as a 16-bit signed immediate.
104 if (!isIntN(16, Value) && Ctx)
105 Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup");
107 case Mips::fixup_MIPS_PC21_S2:
109 // Forcing a signed division because Value can be negative.
110 Value = (int64_t) Value / 4;
111 // We now check if Value can be encoded as a 21-bit signed immediate.
112 if (!isIntN(21, Value) && Ctx)
113 Ctx->FatalError(Fixup.getLoc(), "out of range PC21 fixup");
115 case Mips::fixup_MIPS_PC26_S2:
117 // Forcing a signed division because Value can be negative.
118 Value = (int64_t) Value / 4;
119 // We now check if Value can be encoded as a 26-bit signed immediate.
120 if (!isIntN(26, Value) && Ctx)
121 Ctx->FatalError(Fixup.getLoc(), "out of range PC26 fixup");
128 MCObjectWriter *MipsAsmBackend::createObjectWriter(raw_ostream &OS) const {
129 return createMipsELFObjectWriter(OS,
130 MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
133 // Little-endian fixup data byte ordering:
134 // mips32r2: a | b | x | x
135 // microMIPS: x | x | a | b
137 static bool needsMMLEByteOrder(unsigned Kind) {
138 return Kind >= Mips::fixup_MICROMIPS_26_S1 &&
139 Kind < Mips::LastTargetFixupKind;
142 // Calculate index for microMIPS specific little endian byte order
143 static unsigned calculateMMLEIndex(unsigned i) {
144 assert(i <= 3 && "Index out of range!");
146 return (1 - i / 2) * 2 + i % 2;
149 /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
150 /// data fragment, at the offset specified by the fixup and following the
151 /// fixup kind as appropriate.
152 void MipsAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
153 unsigned DataSize, uint64_t Value,
154 bool IsPCRel) const {
155 MCFixupKind Kind = Fixup.getKind();
156 Value = adjustFixupValue(Fixup, Value);
159 return; // Doesn't change encoding.
161 // Where do we start in the object
162 unsigned Offset = Fixup.getOffset();
163 // Number of bytes we need to fixup
164 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
165 // Used to point to big endian bytes
168 switch ((unsigned)Kind) {
170 case Mips::fixup_Mips_16:
174 case Mips::fixup_Mips_64:
183 // Grab current value, if any, from bits.
186 bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind);
188 for (unsigned i = 0; i != NumBytes; ++i) {
189 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
191 : (FullSize - 1 - i);
192 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
195 uint64_t Mask = ((uint64_t)(-1) >>
196 (64 - getFixupKindInfo(Kind).TargetSize));
197 CurVal |= Value & Mask;
199 // Write out the fixed up bytes back to the code/data bits.
200 for (unsigned i = 0; i != NumBytes; ++i) {
201 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
203 : (FullSize - 1 - i);
204 Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
208 const MCFixupKindInfo &MipsAsmBackend::
209 getFixupKindInfo(MCFixupKind Kind) const {
210 const static MCFixupKindInfo LittleEndianInfos[Mips::NumTargetFixupKinds] = {
211 // This table *must* be in same the order of fixup_* kinds in
214 // name offset bits flags
215 { "fixup_Mips_16", 0, 16, 0 },
216 { "fixup_Mips_32", 0, 32, 0 },
217 { "fixup_Mips_REL32", 0, 32, 0 },
218 { "fixup_Mips_26", 0, 26, 0 },
219 { "fixup_Mips_HI16", 0, 16, 0 },
220 { "fixup_Mips_LO16", 0, 16, 0 },
221 { "fixup_Mips_GPREL16", 0, 16, 0 },
222 { "fixup_Mips_LITERAL", 0, 16, 0 },
223 { "fixup_Mips_GOT_Global", 0, 16, 0 },
224 { "fixup_Mips_GOT_Local", 0, 16, 0 },
225 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
226 { "fixup_Mips_CALL16", 0, 16, 0 },
227 { "fixup_Mips_GPREL32", 0, 32, 0 },
228 { "fixup_Mips_SHIFT5", 6, 5, 0 },
229 { "fixup_Mips_SHIFT6", 6, 5, 0 },
230 { "fixup_Mips_64", 0, 64, 0 },
231 { "fixup_Mips_TLSGD", 0, 16, 0 },
232 { "fixup_Mips_GOTTPREL", 0, 16, 0 },
233 { "fixup_Mips_TPREL_HI", 0, 16, 0 },
234 { "fixup_Mips_TPREL_LO", 0, 16, 0 },
235 { "fixup_Mips_TLSLDM", 0, 16, 0 },
236 { "fixup_Mips_DTPREL_HI", 0, 16, 0 },
237 { "fixup_Mips_DTPREL_LO", 0, 16, 0 },
238 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
239 { "fixup_Mips_GPOFF_HI", 0, 16, 0 },
240 { "fixup_Mips_GPOFF_LO", 0, 16, 0 },
241 { "fixup_Mips_GOT_PAGE", 0, 16, 0 },
242 { "fixup_Mips_GOT_OFST", 0, 16, 0 },
243 { "fixup_Mips_GOT_DISP", 0, 16, 0 },
244 { "fixup_Mips_HIGHER", 0, 16, 0 },
245 { "fixup_Mips_HIGHEST", 0, 16, 0 },
246 { "fixup_Mips_GOT_HI16", 0, 16, 0 },
247 { "fixup_Mips_GOT_LO16", 0, 16, 0 },
248 { "fixup_Mips_CALL_HI16", 0, 16, 0 },
249 { "fixup_Mips_CALL_LO16", 0, 16, 0 },
250 { "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
251 { "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
252 { "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
253 { "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
254 { "fixup_MICROMIPS_26_S1", 0, 26, 0 },
255 { "fixup_MICROMIPS_HI16", 0, 16, 0 },
256 { "fixup_MICROMIPS_LO16", 0, 16, 0 },
257 { "fixup_MICROMIPS_GOT16", 0, 16, 0 },
258 { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
259 { "fixup_MICROMIPS_CALL16", 0, 16, 0 },
260 { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 },
261 { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 },
262 { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 },
263 { "fixup_MICROMIPS_TLS_GD", 0, 16, 0 },
264 { "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 },
265 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 },
266 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 },
267 { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 },
268 { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 }
271 const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = {
272 // This table *must* be in same the order of fixup_* kinds in
275 // name offset bits flags
276 { "fixup_Mips_16", 16, 16, 0 },
277 { "fixup_Mips_32", 0, 32, 0 },
278 { "fixup_Mips_REL32", 0, 32, 0 },
279 { "fixup_Mips_26", 6, 26, 0 },
280 { "fixup_Mips_HI16", 16, 16, 0 },
281 { "fixup_Mips_LO16", 16, 16, 0 },
282 { "fixup_Mips_GPREL16", 16, 16, 0 },
283 { "fixup_Mips_LITERAL", 16, 16, 0 },
284 { "fixup_Mips_GOT_Global", 16, 16, 0 },
285 { "fixup_Mips_GOT_Local", 16, 16, 0 },
286 { "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
287 { "fixup_Mips_CALL16", 16, 16, 0 },
288 { "fixup_Mips_GPREL32", 0, 32, 0 },
289 { "fixup_Mips_SHIFT5", 21, 5, 0 },
290 { "fixup_Mips_SHIFT6", 21, 5, 0 },
291 { "fixup_Mips_64", 0, 64, 0 },
292 { "fixup_Mips_TLSGD", 16, 16, 0 },
293 { "fixup_Mips_GOTTPREL", 16, 16, 0 },
294 { "fixup_Mips_TPREL_HI", 16, 16, 0 },
295 { "fixup_Mips_TPREL_LO", 16, 16, 0 },
296 { "fixup_Mips_TLSLDM", 16, 16, 0 },
297 { "fixup_Mips_DTPREL_HI", 16, 16, 0 },
298 { "fixup_Mips_DTPREL_LO", 16, 16, 0 },
299 { "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel },
300 { "fixup_Mips_GPOFF_HI", 16, 16, 0 },
301 { "fixup_Mips_GPOFF_LO", 16, 16, 0 },
302 { "fixup_Mips_GOT_PAGE", 16, 16, 0 },
303 { "fixup_Mips_GOT_OFST", 16, 16, 0 },
304 { "fixup_Mips_GOT_DISP", 16, 16, 0 },
305 { "fixup_Mips_HIGHER", 16, 16, 0 },
306 { "fixup_Mips_HIGHEST", 16, 16, 0 },
307 { "fixup_Mips_GOT_HI16", 16, 16, 0 },
308 { "fixup_Mips_GOT_LO16", 16, 16, 0 },
309 { "fixup_Mips_CALL_HI16", 16, 16, 0 },
310 { "fixup_Mips_CALL_LO16", 16, 16, 0 },
311 { "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel },
312 { "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
313 { "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
314 { "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
315 { "fixup_MICROMIPS_26_S1", 6, 26, 0 },
316 { "fixup_MICROMIPS_HI16", 16, 16, 0 },
317 { "fixup_MICROMIPS_LO16", 16, 16, 0 },
318 { "fixup_MICROMIPS_GOT16", 16, 16, 0 },
319 { "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel },
320 { "fixup_MICROMIPS_CALL16", 16, 16, 0 },
321 { "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 },
322 { "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 },
323 { "fixup_MICROMIPS_GOT_OFST", 16, 16, 0 },
324 { "fixup_MICROMIPS_TLS_GD", 16, 16, 0 },
325 { "fixup_MICROMIPS_TLS_LDM", 16, 16, 0 },
326 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 },
327 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 },
328 { "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 },
329 { "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 }
332 if (Kind < FirstTargetFixupKind)
333 return MCAsmBackend::getFixupKindInfo(Kind);
335 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
339 return LittleEndianInfos[Kind - FirstTargetFixupKind];
340 return BigEndianInfos[Kind - FirstTargetFixupKind];
343 /// WriteNopData - Write an (optimal) nop sequence of Count bytes
344 /// to the given output. If the target cannot generate such a sequence,
345 /// it should return an error.
347 /// \return - True on success.
348 bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
349 // Check for a less than instruction size number of bytes
350 // FIXME: 16 bit instructions are not handled yet here.
351 // We shouldn't be using a hard coded number for instruction size.
352 if (Count % 4) return false;
354 uint64_t NumNops = Count / 4;
355 for (uint64_t i = 0; i != NumNops; ++i)
360 /// processFixupValue - Target hook to process the literal value of a fixup
362 void MipsAsmBackend::processFixupValue(const MCAssembler &Asm,
363 const MCAsmLayout &Layout,
364 const MCFixup &Fixup,
365 const MCFragment *DF,
366 const MCValue &Target,
369 // At this point we'll ignore the value returned by adjustFixupValue as
370 // we are only checking if the fixup can be applied correctly. We have
371 // access to MCContext from here which allows us to report a fatal error
372 // with *possibly* a source code location.
373 (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
377 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
378 const MCRegisterInfo &MRI,
381 return new MipsAsmBackend(T, Triple(TT).getOS(),
382 /*IsLittle*/true, /*Is64Bit*/false);
385 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T,
386 const MCRegisterInfo &MRI,
389 return new MipsAsmBackend(T, Triple(TT).getOS(),
390 /*IsLittle*/false, /*Is64Bit*/false);
393 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T,
394 const MCRegisterInfo &MRI,
397 return new MipsAsmBackend(T, Triple(TT).getOS(),
398 /*IsLittle*/true, /*Is64Bit*/true);
401 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
402 const MCRegisterInfo &MRI,
405 return new MipsAsmBackend(T, Triple(TT).getOS(),
406 /*IsLittle*/false, /*Is64Bit*/true);