1 //===-- MipsBaseInfo.h - Top level definitions for ARM ------- --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains small standalone helper functions and enum definitions for
11 // the Mips target useful for the compiler back-end and the MC libraries.
13 //===----------------------------------------------------------------------===//
14 #ifndef MIPSBASEINFO_H
15 #define MIPSBASEINFO_H
17 #include "MipsMCTargetDesc.h"
18 #include "llvm/Support/DataTypes.h"
19 #include "llvm/Support/ErrorHandling.h"
23 /// MipsII - This namespace holds all of the target specific flags that
24 /// instruction info tracks.
27 /// Target Operand Flag enum.
29 //===------------------------------------------------------------------===//
30 // Mips Specific MachineOperand flags.
34 /// MO_GOT16 - Represents the offset into the global offset table at which
35 /// the address the relocation entry symbol resides during execution.
39 /// MO_GOT_CALL - Represents the offset into the global offset table at
40 /// which the address of a call site relocation entry symbol resides
41 /// during execution. This is different from the above since this flag
42 /// can only be present in call instructions.
45 /// MO_GPREL - Represents the offset from the current gp value to be used
46 /// for the relocatable object file being produced.
49 /// MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol
54 /// MO_TLSGD - Represents the offset into the global offset table at which
55 // the module ID and TSL block offset reside during execution (General
59 /// MO_TLSLDM - Represents the offset into the global offset table at which
60 // the module ID and TSL block offset reside during execution (Local
66 /// MO_GOTTPREL - Represents the offset from the thread pointer (Initial
70 /// MO_TPREL_HI/LO - Represents the hi and low part of the offset from
71 // the thread pointer (Local Exec TLS).
84 //===------------------------------------------------------------------===//
85 // Instruction encodings. These are the standard/most common forms for
89 // Pseudo - This represents an instruction that is a pseudo instruction
90 // or one that has not been implemented yet. It is illegal to code generate
91 // it, but tolerated for intermediate implementation stages.
94 /// FrmR - This form is for instructions of the format R.
96 /// FrmI - This form is for instructions of the format I.
98 /// FrmJ - This form is for instructions of the format J.
100 /// FrmFR - This form is for instructions of the format FR.
102 /// FrmFI - This form is for instructions of the format FI.
104 /// FrmOther - This form is for instructions that have no specific format.
112 /// getMipsRegisterNumbering - Given the enum value for some register,
113 /// return the number that it corresponds to.
114 inline static unsigned getMipsRegisterNumbering(unsigned RegEnum)
117 case Mips::ZERO: case Mips::ZERO_64: case Mips::F0: case Mips::D0_64:
120 case Mips::AT: case Mips::AT_64: case Mips::F1: case Mips::D1_64:
122 case Mips::V0: case Mips::V0_64: case Mips::F2: case Mips::D2_64:
125 case Mips::V1: case Mips::V1_64: case Mips::F3: case Mips::D3_64:
127 case Mips::A0: case Mips::A0_64: case Mips::F4: case Mips::D4_64:
130 case Mips::A1: case Mips::A1_64: case Mips::F5: case Mips::D5_64:
132 case Mips::A2: case Mips::A2_64: case Mips::F6: case Mips::D6_64:
135 case Mips::A3: case Mips::A3_64: case Mips::F7: case Mips::D7_64:
137 case Mips::T0: case Mips::T0_64: case Mips::F8: case Mips::D8_64:
140 case Mips::T1: case Mips::T1_64: case Mips::F9: case Mips::D9_64:
142 case Mips::T2: case Mips::T2_64: case Mips::F10: case Mips::D10_64:
145 case Mips::T3: case Mips::T3_64: case Mips::F11: case Mips::D11_64:
147 case Mips::T4: case Mips::T4_64: case Mips::F12: case Mips::D12_64:
150 case Mips::T5: case Mips::T5_64: case Mips::F13: case Mips::D13_64:
152 case Mips::T6: case Mips::T6_64: case Mips::F14: case Mips::D14_64:
155 case Mips::T7: case Mips::T7_64: case Mips::F15: case Mips::D15_64:
157 case Mips::S0: case Mips::S0_64: case Mips::F16: case Mips::D16_64:
160 case Mips::S1: case Mips::S1_64: case Mips::F17: case Mips::D17_64:
162 case Mips::S2: case Mips::S2_64: case Mips::F18: case Mips::D18_64:
165 case Mips::S3: case Mips::S3_64: case Mips::F19: case Mips::D19_64:
167 case Mips::S4: case Mips::S4_64: case Mips::F20: case Mips::D20_64:
170 case Mips::S5: case Mips::S5_64: case Mips::F21: case Mips::D21_64:
172 case Mips::S6: case Mips::S6_64: case Mips::F22: case Mips::D22_64:
175 case Mips::S7: case Mips::S7_64: case Mips::F23: case Mips::D23_64:
177 case Mips::T8: case Mips::T8_64: case Mips::F24: case Mips::D24_64:
180 case Mips::T9: case Mips::T9_64: case Mips::F25: case Mips::D25_64:
182 case Mips::K0: case Mips::K0_64: case Mips::F26: case Mips::D26_64:
185 case Mips::K1: case Mips::K1_64: case Mips::F27: case Mips::D27_64:
187 case Mips::GP: case Mips::GP_64: case Mips::F28: case Mips::D28_64:
190 case Mips::SP: case Mips::SP_64: case Mips::F29: case Mips::D29_64:
193 case Mips::FP: case Mips::FP_64: case Mips::F30: case Mips::D30_64:
196 case Mips::RA: case Mips::RA_64: case Mips::F31: case Mips::D31_64:
198 default: llvm_unreachable("Unknown register number!");
200 return 0; // Not reached