1 //===-- MipsBaseInfo.h - Top level definitions for ARM ------- --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains small standalone helper functions and enum definitions for
11 // the Mips target useful for the compiler back-end and the MC libraries.
13 //===----------------------------------------------------------------------===//
14 #ifndef MIPSBASEINFO_H
15 #define MIPSBASEINFO_H
17 #include "MipsMCTargetDesc.h"
18 #include "llvm/Support/DataTypes.h"
19 #include "llvm/Support/ErrorHandling.h"
22 /// getMipsRegisterNumbering - Given the enum value for some register,
23 /// return the number that it corresponds to.
24 inline static unsigned getMipsRegisterNumbering(unsigned RegEnum)
27 case Mips::ZERO: case Mips::ZERO_64: case Mips::F0: case Mips::D0_64:
30 case Mips::AT: case Mips::AT_64: case Mips::F1: case Mips::D1_64:
32 case Mips::V0: case Mips::V0_64: case Mips::F2: case Mips::D2_64:
35 case Mips::V1: case Mips::V1_64: case Mips::F3: case Mips::D3_64:
37 case Mips::A0: case Mips::A0_64: case Mips::F4: case Mips::D4_64:
40 case Mips::A1: case Mips::A1_64: case Mips::F5: case Mips::D5_64:
42 case Mips::A2: case Mips::A2_64: case Mips::F6: case Mips::D6_64:
45 case Mips::A3: case Mips::A3_64: case Mips::F7: case Mips::D7_64:
47 case Mips::T0: case Mips::T0_64: case Mips::F8: case Mips::D8_64:
50 case Mips::T1: case Mips::T1_64: case Mips::F9: case Mips::D9_64:
52 case Mips::T2: case Mips::T2_64: case Mips::F10: case Mips::D10_64:
55 case Mips::T3: case Mips::T3_64: case Mips::F11: case Mips::D11_64:
57 case Mips::T4: case Mips::T4_64: case Mips::F12: case Mips::D12_64:
60 case Mips::T5: case Mips::T5_64: case Mips::F13: case Mips::D13_64:
62 case Mips::T6: case Mips::T6_64: case Mips::F14: case Mips::D14_64:
65 case Mips::T7: case Mips::T7_64: case Mips::F15: case Mips::D15_64:
67 case Mips::S0: case Mips::S0_64: case Mips::F16: case Mips::D16_64:
70 case Mips::S1: case Mips::S1_64: case Mips::F17: case Mips::D17_64:
72 case Mips::S2: case Mips::S2_64: case Mips::F18: case Mips::D18_64:
75 case Mips::S3: case Mips::S3_64: case Mips::F19: case Mips::D19_64:
77 case Mips::S4: case Mips::S4_64: case Mips::F20: case Mips::D20_64:
80 case Mips::S5: case Mips::S5_64: case Mips::F21: case Mips::D21_64:
82 case Mips::S6: case Mips::S6_64: case Mips::F22: case Mips::D22_64:
85 case Mips::S7: case Mips::S7_64: case Mips::F23: case Mips::D23_64:
87 case Mips::T8: case Mips::T8_64: case Mips::F24: case Mips::D24_64:
90 case Mips::T9: case Mips::T9_64: case Mips::F25: case Mips::D25_64:
92 case Mips::K0: case Mips::K0_64: case Mips::F26: case Mips::D26_64:
95 case Mips::K1: case Mips::K1_64: case Mips::F27: case Mips::D27_64:
97 case Mips::GP: case Mips::GP_64: case Mips::F28: case Mips::D28_64:
100 case Mips::SP: case Mips::SP_64: case Mips::F29: case Mips::D29_64:
102 case Mips::FP: case Mips::FP_64: case Mips::F30: case Mips::D30_64:
105 case Mips::RA: case Mips::RA_64: case Mips::F31: case Mips::D31_64:
107 default: llvm_unreachable("Unknown register number!");
109 return 0; // Not reached