1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MCTargetDesc/MipsFixupKinds.h"
17 #include "MCTargetDesc/MipsMCTargetDesc.h"
18 #include "llvm/ADT/APFloat.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/Support/raw_ostream.h"
29 #define GET_INSTRMAP_INFO
30 #include "MipsGenInstrInfo.inc"
35 class MipsMCCodeEmitter : public MCCodeEmitter {
36 MipsMCCodeEmitter(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
37 void operator=(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
38 const MCInstrInfo &MCII;
40 const MCSubtargetInfo &STI;
45 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_,
46 const MCSubtargetInfo &sti, bool IsLittle) :
47 MCII(mcii), Ctx(Ctx_), STI (sti), IsLittleEndian(IsLittle) {
48 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
51 ~MipsMCCodeEmitter() {}
53 void EmitByte(unsigned char C, raw_ostream &OS) const {
57 void EmitInstruction(uint64_t Val, unsigned Size, raw_ostream &OS) const {
58 // Output the instruction encoding in little endian byte order.
59 // Little-endian byte ordering:
60 // mips32r2: 4 | 3 | 2 | 1
61 // microMIPS: 2 | 1 | 4 | 3
62 if (IsLittleEndian && Size == 4 && IsMicroMips) {
63 EmitInstruction(Val>>16, 2, OS);
64 EmitInstruction(Val, 2, OS);
66 for (unsigned i = 0; i < Size; ++i) {
67 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
68 EmitByte((Val >> Shift) & 0xff, OS);
73 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
74 SmallVectorImpl<MCFixup> &Fixups) const;
76 // getBinaryCodeForInstr - TableGen'erated function for getting the
77 // binary encoding for an instruction.
78 uint64_t getBinaryCodeForInstr(const MCInst &MI,
79 SmallVectorImpl<MCFixup> &Fixups) const;
81 // getBranchJumpOpValue - Return binary encoding of the jump
82 // target operand. If the machine operand requires relocation,
83 // record the relocation and return zero.
84 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
85 SmallVectorImpl<MCFixup> &Fixups) const;
87 // getBranchJumpOpValueMM - Return binary encoding of the microMIPS jump
88 // target operand. If the machine operand requires relocation,
89 // record the relocation and return zero.
90 unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
91 SmallVectorImpl<MCFixup> &Fixups) const;
93 // getBranchTargetOpValue - Return binary encoding of the branch
94 // target operand. If the machine operand requires relocation,
95 // record the relocation and return zero.
96 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
97 SmallVectorImpl<MCFixup> &Fixups) const;
99 // getBranchTargetOpValue - Return binary encoding of the microMIPS branch
100 // target operand. If the machine operand requires relocation,
101 // record the relocation and return zero.
102 unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
103 SmallVectorImpl<MCFixup> &Fixups) const;
105 // getMachineOpValue - Return binary encoding of operand. If the machin
106 // operand requires relocation, record the relocation and return zero.
107 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
108 SmallVectorImpl<MCFixup> &Fixups) const;
110 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
111 SmallVectorImpl<MCFixup> &Fixups) const;
112 unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
113 SmallVectorImpl<MCFixup> &Fixups) const;
114 unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
115 SmallVectorImpl<MCFixup> &Fixups) const;
116 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
117 SmallVectorImpl<MCFixup> &Fixups) const;
120 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups) const;
122 }; // class MipsMCCodeEmitter
125 MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
126 const MCRegisterInfo &MRI,
127 const MCSubtargetInfo &STI,
130 return new MipsMCCodeEmitter(MCII, Ctx, STI, false);
133 MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
134 const MCRegisterInfo &MRI,
135 const MCSubtargetInfo &STI,
138 return new MipsMCCodeEmitter(MCII, Ctx, STI, true);
142 // If the D<shift> instruction has a shift amount that is greater
143 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
144 static void LowerLargeShift(MCInst& Inst) {
146 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
147 assert(Inst.getOperand(2).isImm());
149 int64_t Shift = Inst.getOperand(2).getImm();
151 return; // Do nothing
155 Inst.getOperand(2).setImm(Shift);
157 switch (Inst.getOpcode()) {
159 // Calling function is not synchronized
160 llvm_unreachable("Unexpected shift instruction");
162 Inst.setOpcode(Mips::DSLL32);
165 Inst.setOpcode(Mips::DSRL32);
168 Inst.setOpcode(Mips::DSRA32);
171 Inst.setOpcode(Mips::DROTR32);
176 // Pick a DEXT or DINS instruction variant based on the pos and size operands
177 static void LowerDextDins(MCInst& InstIn) {
178 int Opcode = InstIn.getOpcode();
180 if (Opcode == Mips::DEXT)
181 assert(InstIn.getNumOperands() == 4 &&
182 "Invalid no. of machine operands for DEXT!");
183 else // Only DEXT and DINS are possible
184 assert(InstIn.getNumOperands() == 5 &&
185 "Invalid no. of machine operands for DINS!");
187 assert(InstIn.getOperand(2).isImm());
188 int64_t pos = InstIn.getOperand(2).getImm();
189 assert(InstIn.getOperand(3).isImm());
190 int64_t size = InstIn.getOperand(3).getImm();
193 if (pos < 32) // DEXT/DINS, do nothing
196 InstIn.getOperand(2).setImm(pos - 32);
197 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
201 assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
202 InstIn.getOperand(3).setImm(size - 32);
203 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
207 /// EncodeInstruction - Emit the instruction.
208 /// Size the instruction with Desc.getSize().
209 void MipsMCCodeEmitter::
210 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
211 SmallVectorImpl<MCFixup> &Fixups) const
214 // Non-pseudo instructions that get changed for direct object
215 // only based on operand values.
216 // If this list of instructions get much longer we will move
217 // the check to a function call. Until then, this is more efficient.
219 switch (MI.getOpcode()) {
220 // If shift amount is >= 32 it the inst needs to be lowered further
225 LowerLargeShift(TmpInst);
227 // Double extract instruction is chosen by pos and size operands
230 LowerDextDins(TmpInst);
233 unsigned long N = Fixups.size();
234 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups);
236 // Check for unimplemented opcodes.
237 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
238 // so we have to special check for them.
239 unsigned Opcode = TmpInst.getOpcode();
240 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
241 llvm_unreachable("unimplemented opcode in EncodeInstruction()");
243 if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
244 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
245 if (NewOpcode != -1) {
246 if (Fixups.size() > N)
249 TmpInst.setOpcode (NewOpcode);
250 Binary = getBinaryCodeForInstr(TmpInst, Fixups);
254 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
256 // Get byte count of instruction
257 unsigned Size = Desc.getSize();
259 llvm_unreachable("Desc.getSize() returns 0");
261 EmitInstruction(Binary, Size, OS);
264 /// getBranchTargetOpValue - Return binary encoding of the branch
265 /// target operand. If the machine operand requires relocation,
266 /// record the relocation and return zero.
267 unsigned MipsMCCodeEmitter::
268 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
269 SmallVectorImpl<MCFixup> &Fixups) const {
271 const MCOperand &MO = MI.getOperand(OpNo);
273 // If the destination is an immediate, divide by 4.
274 if (MO.isImm()) return MO.getImm() >> 2;
276 assert(MO.isExpr() &&
277 "getBranchTargetOpValue expects only expressions or immediates");
279 const MCExpr *Expr = MO.getExpr();
280 Fixups.push_back(MCFixup::Create(0, Expr,
281 MCFixupKind(Mips::fixup_Mips_PC16)));
285 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
286 /// target operand. If the machine operand requires relocation,
287 /// record the relocation and return zero.
288 unsigned MipsMCCodeEmitter::
289 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
290 SmallVectorImpl<MCFixup> &Fixups) const {
292 const MCOperand &MO = MI.getOperand(OpNo);
294 // If the destination is an immediate, divide by 2.
295 if (MO.isImm()) return MO.getImm() >> 1;
297 assert(MO.isExpr() &&
298 "getBranchTargetOpValueMM expects only expressions or immediates");
300 const MCExpr *Expr = MO.getExpr();
301 Fixups.push_back(MCFixup::Create(0, Expr,
303 fixup_MICROMIPS_PC16_S1)));
307 /// getJumpTargetOpValue - Return binary encoding of the jump
308 /// target operand. If the machine operand requires relocation,
309 /// record the relocation and return zero.
310 unsigned MipsMCCodeEmitter::
311 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
312 SmallVectorImpl<MCFixup> &Fixups) const {
314 const MCOperand &MO = MI.getOperand(OpNo);
315 // If the destination is an immediate, divide by 4.
316 if (MO.isImm()) return MO.getImm()>>2;
318 assert(MO.isExpr() &&
319 "getJumpTargetOpValue expects only expressions or an immediate");
321 const MCExpr *Expr = MO.getExpr();
322 Fixups.push_back(MCFixup::Create(0, Expr,
323 MCFixupKind(Mips::fixup_Mips_26)));
327 unsigned MipsMCCodeEmitter::
328 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
329 SmallVectorImpl<MCFixup> &Fixups) const {
331 const MCOperand &MO = MI.getOperand(OpNo);
332 // If the destination is an immediate, divide by 2.
333 if (MO.isImm()) return MO.getImm() >> 1;
335 assert(MO.isExpr() &&
336 "getJumpTargetOpValueMM expects only expressions or an immediate");
338 const MCExpr *Expr = MO.getExpr();
339 Fixups.push_back(MCFixup::Create(0, Expr,
340 MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
344 unsigned MipsMCCodeEmitter::
345 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups) const {
348 if (Expr->EvaluateAsAbsolute(Res))
351 MCExpr::ExprKind Kind = Expr->getKind();
352 if (Kind == MCExpr::Constant) {
353 return cast<MCConstantExpr>(Expr)->getValue();
356 if (Kind == MCExpr::Binary) {
357 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups);
358 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups);
361 if (Kind == MCExpr::SymbolRef) {
362 Mips::Fixups FixupKind = Mips::Fixups(0);
364 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
365 default: llvm_unreachable("Unknown fixup kind!");
367 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
368 FixupKind = Mips::fixup_Mips_GPOFF_HI;
370 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
371 FixupKind = Mips::fixup_Mips_GPOFF_LO;
373 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
374 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT_PAGE
375 : Mips::fixup_Mips_GOT_PAGE;
377 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
378 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT_OFST
379 : Mips::fixup_Mips_GOT_OFST;
381 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
382 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT_DISP
383 : Mips::fixup_Mips_GOT_DISP;
385 case MCSymbolRefExpr::VK_Mips_GPREL:
386 FixupKind = Mips::fixup_Mips_GPREL16;
388 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
389 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_CALL16
390 : Mips::fixup_Mips_CALL16;
392 case MCSymbolRefExpr::VK_Mips_GOT16:
393 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT16
394 : Mips::fixup_Mips_GOT_Global;
396 case MCSymbolRefExpr::VK_Mips_GOT:
397 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT16
398 : Mips::fixup_Mips_GOT_Local;
400 case MCSymbolRefExpr::VK_Mips_ABS_HI:
401 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_HI16
402 : Mips::fixup_Mips_HI16;
404 case MCSymbolRefExpr::VK_Mips_ABS_LO:
405 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_LO16
406 : Mips::fixup_Mips_LO16;
408 case MCSymbolRefExpr::VK_Mips_TLSGD:
409 FixupKind = Mips::fixup_Mips_TLSGD;
411 case MCSymbolRefExpr::VK_Mips_TLSLDM:
412 FixupKind = Mips::fixup_Mips_TLSLDM;
414 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
415 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
416 : Mips::fixup_Mips_DTPREL_HI;
418 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
419 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
420 : Mips::fixup_Mips_DTPREL_LO;
422 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
423 FixupKind = Mips::fixup_Mips_GOTTPREL;
425 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
426 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
427 : Mips::fixup_Mips_TPREL_HI;
429 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
430 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
431 : Mips::fixup_Mips_TPREL_LO;
433 case MCSymbolRefExpr::VK_Mips_HIGHER:
434 FixupKind = Mips::fixup_Mips_HIGHER;
436 case MCSymbolRefExpr::VK_Mips_HIGHEST:
437 FixupKind = Mips::fixup_Mips_HIGHEST;
439 case MCSymbolRefExpr::VK_Mips_GOT_HI16:
440 FixupKind = Mips::fixup_Mips_GOT_HI16;
442 case MCSymbolRefExpr::VK_Mips_GOT_LO16:
443 FixupKind = Mips::fixup_Mips_GOT_LO16;
445 case MCSymbolRefExpr::VK_Mips_CALL_HI16:
446 FixupKind = Mips::fixup_Mips_CALL_HI16;
448 case MCSymbolRefExpr::VK_Mips_CALL_LO16:
449 FixupKind = Mips::fixup_Mips_CALL_LO16;
453 Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
459 /// getMachineOpValue - Return binary encoding of operand. If the machine
460 /// operand requires relocation, record the relocation and return zero.
461 unsigned MipsMCCodeEmitter::
462 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
463 SmallVectorImpl<MCFixup> &Fixups) const {
465 unsigned Reg = MO.getReg();
466 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
468 } else if (MO.isImm()) {
469 return static_cast<unsigned>(MO.getImm());
470 } else if (MO.isFPImm()) {
471 return static_cast<unsigned>(APFloat(MO.getFPImm())
472 .bitcastToAPInt().getHiBits(32).getLimitedValue());
474 // MO must be an Expr.
476 return getExprOpValue(MO.getExpr(),Fixups);
479 /// getMemEncoding - Return binary encoding of memory related operand.
480 /// If the offset operand requires relocation, record the relocation.
482 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
483 SmallVectorImpl<MCFixup> &Fixups) const {
484 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
485 assert(MI.getOperand(OpNo).isReg());
486 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
487 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
489 return (OffBits & 0xFFFF) | RegBits;
492 unsigned MipsMCCodeEmitter::
493 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
494 SmallVectorImpl<MCFixup> &Fixups) const {
495 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
496 assert(MI.getOperand(OpNo).isReg());
497 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups) << 16;
498 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
500 return (OffBits & 0x0FFF) | RegBits;
504 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
505 SmallVectorImpl<MCFixup> &Fixups) const {
506 assert(MI.getOperand(OpNo).isImm());
507 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
508 return SizeEncoding - 1;
511 // FIXME: should be called getMSBEncoding
514 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
515 SmallVectorImpl<MCFixup> &Fixups) const {
516 assert(MI.getOperand(OpNo-1).isImm());
517 assert(MI.getOperand(OpNo).isImm());
518 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
519 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
521 return Position + Size - 1;
524 #include "MipsGenMCCodeEmitter.inc"