1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
15 #include "MipsMCCodeEmitter.h"
16 #include "MCTargetDesc/MipsFixupKinds.h"
17 #include "MCTargetDesc/MipsMCExpr.h"
18 #include "MCTargetDesc/MipsMCTargetDesc.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCFixup.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "mccodeemitter"
31 #define GET_INSTRMAP_INFO
32 #include "MipsGenInstrInfo.inc"
33 #undef GET_INSTRMAP_INFO
36 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
37 const MCRegisterInfo &MRI,
38 const MCSubtargetInfo &STI,
40 return new MipsMCCodeEmitter(MCII, Ctx, false);
43 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
44 const MCRegisterInfo &MRI,
45 const MCSubtargetInfo &STI,
47 return new MipsMCCodeEmitter(MCII, Ctx, true);
49 } // End of namespace llvm.
51 // If the D<shift> instruction has a shift amount that is greater
52 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
53 static void LowerLargeShift(MCInst& Inst) {
55 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
56 assert(Inst.getOperand(2).isImm());
58 int64_t Shift = Inst.getOperand(2).getImm();
64 Inst.getOperand(2).setImm(Shift);
66 switch (Inst.getOpcode()) {
68 // Calling function is not synchronized
69 llvm_unreachable("Unexpected shift instruction");
71 Inst.setOpcode(Mips::DSLL32);
74 Inst.setOpcode(Mips::DSRL32);
77 Inst.setOpcode(Mips::DSRA32);
80 Inst.setOpcode(Mips::DROTR32);
85 // Pick a DEXT or DINS instruction variant based on the pos and size operands
86 static void LowerDextDins(MCInst& InstIn) {
87 int Opcode = InstIn.getOpcode();
89 if (Opcode == Mips::DEXT)
90 assert(InstIn.getNumOperands() == 4 &&
91 "Invalid no. of machine operands for DEXT!");
92 else // Only DEXT and DINS are possible
93 assert(InstIn.getNumOperands() == 5 &&
94 "Invalid no. of machine operands for DINS!");
96 assert(InstIn.getOperand(2).isImm());
97 int64_t pos = InstIn.getOperand(2).getImm();
98 assert(InstIn.getOperand(3).isImm());
99 int64_t size = InstIn.getOperand(3).getImm();
102 if (pos < 32) // DEXT/DINS, do nothing
105 InstIn.getOperand(2).setImm(pos - 32);
106 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
110 assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
111 InstIn.getOperand(3).setImm(size - 32);
112 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
116 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
117 return STI.getFeatureBits() & Mips::FeatureMicroMips;
120 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
124 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
125 const MCSubtargetInfo &STI,
126 raw_ostream &OS) const {
127 // Output the instruction encoding in little endian byte order.
128 // Little-endian byte ordering:
129 // mips32r2: 4 | 3 | 2 | 1
130 // microMIPS: 2 | 1 | 4 | 3
131 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
132 EmitInstruction(Val >> 16, 2, STI, OS);
133 EmitInstruction(Val, 2, STI, OS);
135 for (unsigned i = 0; i < Size; ++i) {
136 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
137 EmitByte((Val >> Shift) & 0xff, OS);
142 /// EncodeInstruction - Emit the instruction.
143 /// Size the instruction with Desc.getSize().
144 void MipsMCCodeEmitter::
145 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
146 SmallVectorImpl<MCFixup> &Fixups,
147 const MCSubtargetInfo &STI) const
150 // Non-pseudo instructions that get changed for direct object
151 // only based on operand values.
152 // If this list of instructions get much longer we will move
153 // the check to a function call. Until then, this is more efficient.
155 switch (MI.getOpcode()) {
156 // If shift amount is >= 32 it the inst needs to be lowered further
161 LowerLargeShift(TmpInst);
163 // Double extract instruction is chosen by pos and size operands
166 LowerDextDins(TmpInst);
169 unsigned long N = Fixups.size();
170 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
172 // Check for unimplemented opcodes.
173 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
174 // so we have to special check for them.
175 unsigned Opcode = TmpInst.getOpcode();
176 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
177 (Opcode != Mips::SLL_MM) && !Binary)
178 llvm_unreachable("unimplemented opcode in EncodeInstruction()");
180 if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
181 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
182 if (NewOpcode != -1) {
183 if (Fixups.size() > N)
186 TmpInst.setOpcode (NewOpcode);
187 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
191 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
193 // Get byte count of instruction
194 unsigned Size = Desc.getSize();
196 llvm_unreachable("Desc.getSize() returns 0");
198 EmitInstruction(Binary, Size, STI, OS);
201 /// getBranchTargetOpValue - Return binary encoding of the branch
202 /// target operand. If the machine operand requires relocation,
203 /// record the relocation and return zero.
204 unsigned MipsMCCodeEmitter::
205 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
206 SmallVectorImpl<MCFixup> &Fixups,
207 const MCSubtargetInfo &STI) const {
209 const MCOperand &MO = MI.getOperand(OpNo);
211 // If the destination is an immediate, divide by 4.
212 if (MO.isImm()) return MO.getImm() >> 2;
214 assert(MO.isExpr() &&
215 "getBranchTargetOpValue expects only expressions or immediates");
217 const MCExpr *Expr = MO.getExpr();
218 Fixups.push_back(MCFixup::Create(0, Expr,
219 MCFixupKind(Mips::fixup_Mips_PC16)));
223 /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch
224 /// target operand. If the machine operand requires relocation,
225 /// record the relocation and return zero.
226 unsigned MipsMCCodeEmitter::
227 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
228 SmallVectorImpl<MCFixup> &Fixups,
229 const MCSubtargetInfo &STI) const {
231 const MCOperand &MO = MI.getOperand(OpNo);
233 // If the destination is an immediate, divide by 2.
234 if (MO.isImm()) return MO.getImm() >> 1;
236 assert(MO.isExpr() &&
237 "getBranchTargetOpValueMM expects only expressions or immediates");
239 const MCExpr *Expr = MO.getExpr();
240 Fixups.push_back(MCFixup::Create(0, Expr,
241 MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
245 /// getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS
246 /// 10-bit branch target operand. If the machine operand requires relocation,
247 /// record the relocation and return zero.
248 unsigned MipsMCCodeEmitter::
249 getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
250 SmallVectorImpl<MCFixup> &Fixups,
251 const MCSubtargetInfo &STI) const {
253 const MCOperand &MO = MI.getOperand(OpNo);
255 // If the destination is an immediate, divide by 2.
256 if (MO.isImm()) return MO.getImm() >> 1;
258 assert(MO.isExpr() &&
259 "getBranchTargetOpValuePC10 expects only expressions or immediates");
261 const MCExpr *Expr = MO.getExpr();
262 Fixups.push_back(MCFixup::Create(0, Expr,
263 MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
267 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
268 /// target operand. If the machine operand requires relocation,
269 /// record the relocation and return zero.
270 unsigned MipsMCCodeEmitter::
271 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
272 SmallVectorImpl<MCFixup> &Fixups,
273 const MCSubtargetInfo &STI) const {
275 const MCOperand &MO = MI.getOperand(OpNo);
277 // If the destination is an immediate, divide by 2.
278 if (MO.isImm()) return MO.getImm() >> 1;
280 assert(MO.isExpr() &&
281 "getBranchTargetOpValueMM expects only expressions or immediates");
283 const MCExpr *Expr = MO.getExpr();
284 Fixups.push_back(MCFixup::Create(0, Expr,
286 fixup_MICROMIPS_PC16_S1)));
290 /// getBranchTarget21OpValue - Return binary encoding of the branch
291 /// target operand. If the machine operand requires relocation,
292 /// record the relocation and return zero.
293 unsigned MipsMCCodeEmitter::
294 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
295 SmallVectorImpl<MCFixup> &Fixups,
296 const MCSubtargetInfo &STI) const {
298 const MCOperand &MO = MI.getOperand(OpNo);
300 // If the destination is an immediate, divide by 4.
301 if (MO.isImm()) return MO.getImm() >> 2;
303 assert(MO.isExpr() &&
304 "getBranchTarget21OpValue expects only expressions or immediates");
306 const MCExpr *Expr = MO.getExpr();
307 Fixups.push_back(MCFixup::Create(0, Expr,
308 MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
312 /// getBranchTarget26OpValue - Return binary encoding of the branch
313 /// target operand. If the machine operand requires relocation,
314 /// record the relocation and return zero.
315 unsigned MipsMCCodeEmitter::
316 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
317 SmallVectorImpl<MCFixup> &Fixups,
318 const MCSubtargetInfo &STI) const {
320 const MCOperand &MO = MI.getOperand(OpNo);
322 // If the destination is an immediate, divide by 4.
323 if (MO.isImm()) return MO.getImm() >> 2;
325 assert(MO.isExpr() &&
326 "getBranchTarget26OpValue expects only expressions or immediates");
328 const MCExpr *Expr = MO.getExpr();
329 Fixups.push_back(MCFixup::Create(0, Expr,
330 MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
334 /// getJumpOffset16OpValue - Return binary encoding of the jump
335 /// target operand. If the machine operand requires relocation,
336 /// record the relocation and return zero.
337 unsigned MipsMCCodeEmitter::
338 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
339 SmallVectorImpl<MCFixup> &Fixups,
340 const MCSubtargetInfo &STI) const {
342 const MCOperand &MO = MI.getOperand(OpNo);
344 if (MO.isImm()) return MO.getImm();
346 assert(MO.isExpr() &&
347 "getJumpOffset16OpValue expects only expressions or an immediate");
353 /// getJumpTargetOpValue - Return binary encoding of the jump
354 /// target operand. If the machine operand requires relocation,
355 /// record the relocation and return zero.
356 unsigned MipsMCCodeEmitter::
357 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
358 SmallVectorImpl<MCFixup> &Fixups,
359 const MCSubtargetInfo &STI) const {
361 const MCOperand &MO = MI.getOperand(OpNo);
362 // If the destination is an immediate, divide by 4.
363 if (MO.isImm()) return MO.getImm()>>2;
365 assert(MO.isExpr() &&
366 "getJumpTargetOpValue expects only expressions or an immediate");
368 const MCExpr *Expr = MO.getExpr();
369 Fixups.push_back(MCFixup::Create(0, Expr,
370 MCFixupKind(Mips::fixup_Mips_26)));
374 unsigned MipsMCCodeEmitter::
375 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
376 SmallVectorImpl<MCFixup> &Fixups,
377 const MCSubtargetInfo &STI) const {
379 const MCOperand &MO = MI.getOperand(OpNo);
380 // If the destination is an immediate, divide by 2.
381 if (MO.isImm()) return MO.getImm() >> 1;
383 assert(MO.isExpr() &&
384 "getJumpTargetOpValueMM expects only expressions or an immediate");
386 const MCExpr *Expr = MO.getExpr();
387 Fixups.push_back(MCFixup::Create(0, Expr,
388 MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
392 unsigned MipsMCCodeEmitter::
393 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
394 SmallVectorImpl<MCFixup> &Fixups,
395 const MCSubtargetInfo &STI) const {
397 const MCOperand &MO = MI.getOperand(OpNo);
399 // The immediate is encoded as 'immediate << 2'.
400 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
401 assert((Res & 3) == 0);
405 assert(MO.isExpr() &&
406 "getUImm5Lsl2Encoding expects only expressions or an immediate");
411 unsigned MipsMCCodeEmitter::
412 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
413 SmallVectorImpl<MCFixup> &Fixups,
414 const MCSubtargetInfo &STI) const {
416 const MCOperand &MO = MI.getOperand(OpNo);
418 int Value = MO.getImm();
425 unsigned MipsMCCodeEmitter::
426 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
427 SmallVectorImpl<MCFixup> &Fixups,
428 const MCSubtargetInfo &STI) const {
430 const MCOperand &MO = MI.getOperand(OpNo);
432 unsigned Value = MO.getImm();
439 unsigned MipsMCCodeEmitter::
440 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
441 SmallVectorImpl<MCFixup> &Fixups,
442 const MCSubtargetInfo &STI) const {
444 const MCOperand &MO = MI.getOperand(OpNo);
446 unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
447 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
453 unsigned MipsMCCodeEmitter::
454 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups,
455 const MCSubtargetInfo &STI) const {
458 if (Expr->EvaluateAsAbsolute(Res))
461 MCExpr::ExprKind Kind = Expr->getKind();
462 if (Kind == MCExpr::Constant) {
463 return cast<MCConstantExpr>(Expr)->getValue();
466 if (Kind == MCExpr::Binary) {
467 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
468 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
472 if (Kind == MCExpr::Target) {
473 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
475 Mips::Fixups FixupKind = Mips::Fixups(0);
476 switch (MipsExpr->getKind()) {
477 default: llvm_unreachable("Unsupported fixup kind for target expression!");
478 case MipsMCExpr::VK_Mips_HIGHEST:
479 FixupKind = Mips::fixup_Mips_HIGHEST;
481 case MipsMCExpr::VK_Mips_HIGHER:
482 FixupKind = Mips::fixup_Mips_HIGHER;
484 case MipsMCExpr::VK_Mips_HI:
485 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
486 : Mips::fixup_Mips_HI16;
488 case MipsMCExpr::VK_Mips_LO:
489 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
490 : Mips::fixup_Mips_LO16;
493 Fixups.push_back(MCFixup::Create(0, MipsExpr, MCFixupKind(FixupKind)));
497 if (Kind == MCExpr::SymbolRef) {
498 Mips::Fixups FixupKind = Mips::Fixups(0);
500 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
501 default: llvm_unreachable("Unknown fixup kind!");
503 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
504 FixupKind = Mips::fixup_Mips_GPOFF_HI;
506 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
507 FixupKind = Mips::fixup_Mips_GPOFF_LO;
509 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
510 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
511 : Mips::fixup_Mips_GOT_PAGE;
513 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
514 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
515 : Mips::fixup_Mips_GOT_OFST;
517 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
518 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
519 : Mips::fixup_Mips_GOT_DISP;
521 case MCSymbolRefExpr::VK_Mips_GPREL:
522 FixupKind = Mips::fixup_Mips_GPREL16;
524 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
525 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
526 : Mips::fixup_Mips_CALL16;
528 case MCSymbolRefExpr::VK_Mips_GOT16:
529 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
530 : Mips::fixup_Mips_GOT_Global;
532 case MCSymbolRefExpr::VK_Mips_GOT:
533 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
534 : Mips::fixup_Mips_GOT_Local;
536 case MCSymbolRefExpr::VK_Mips_ABS_HI:
537 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
538 : Mips::fixup_Mips_HI16;
540 case MCSymbolRefExpr::VK_Mips_ABS_LO:
541 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
542 : Mips::fixup_Mips_LO16;
544 case MCSymbolRefExpr::VK_Mips_TLSGD:
545 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
546 : Mips::fixup_Mips_TLSGD;
548 case MCSymbolRefExpr::VK_Mips_TLSLDM:
549 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
550 : Mips::fixup_Mips_TLSLDM;
552 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
553 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
554 : Mips::fixup_Mips_DTPREL_HI;
556 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
557 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
558 : Mips::fixup_Mips_DTPREL_LO;
560 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
561 FixupKind = Mips::fixup_Mips_GOTTPREL;
563 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
564 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
565 : Mips::fixup_Mips_TPREL_HI;
567 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
568 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
569 : Mips::fixup_Mips_TPREL_LO;
571 case MCSymbolRefExpr::VK_Mips_HIGHER:
572 FixupKind = Mips::fixup_Mips_HIGHER;
574 case MCSymbolRefExpr::VK_Mips_HIGHEST:
575 FixupKind = Mips::fixup_Mips_HIGHEST;
577 case MCSymbolRefExpr::VK_Mips_GOT_HI16:
578 FixupKind = Mips::fixup_Mips_GOT_HI16;
580 case MCSymbolRefExpr::VK_Mips_GOT_LO16:
581 FixupKind = Mips::fixup_Mips_GOT_LO16;
583 case MCSymbolRefExpr::VK_Mips_CALL_HI16:
584 FixupKind = Mips::fixup_Mips_CALL_HI16;
586 case MCSymbolRefExpr::VK_Mips_CALL_LO16:
587 FixupKind = Mips::fixup_Mips_CALL_LO16;
589 case MCSymbolRefExpr::VK_Mips_PCREL_HI16:
590 FixupKind = Mips::fixup_MIPS_PCHI16;
592 case MCSymbolRefExpr::VK_Mips_PCREL_LO16:
593 FixupKind = Mips::fixup_MIPS_PCLO16;
597 Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
603 /// getMachineOpValue - Return binary encoding of operand. If the machine
604 /// operand requires relocation, record the relocation and return zero.
605 unsigned MipsMCCodeEmitter::
606 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
607 SmallVectorImpl<MCFixup> &Fixups,
608 const MCSubtargetInfo &STI) const {
610 unsigned Reg = MO.getReg();
611 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
613 } else if (MO.isImm()) {
614 return static_cast<unsigned>(MO.getImm());
615 } else if (MO.isFPImm()) {
616 return static_cast<unsigned>(APFloat(MO.getFPImm())
617 .bitcastToAPInt().getHiBits(32).getLimitedValue());
619 // MO must be an Expr.
621 return getExprOpValue(MO.getExpr(),Fixups, STI);
624 /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
627 MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
628 SmallVectorImpl<MCFixup> &Fixups,
629 const MCSubtargetInfo &STI) const {
630 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
631 assert(MI.getOperand(OpNo).isReg());
632 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
633 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
635 // The immediate field of an LD/ST instruction is scaled which means it must
636 // be divided (when encoding) by the size (in bytes) of the instructions'
642 switch(MI.getOpcode())
645 assert (0 && "Unexpected instruction");
649 // We don't need to scale the offset in this case
665 return (OffBits & 0xFFFF) | RegBits;
668 /// getMemEncoding - Return binary encoding of memory related operand.
669 /// If the offset operand requires relocation, record the relocation.
671 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
672 SmallVectorImpl<MCFixup> &Fixups,
673 const MCSubtargetInfo &STI) const {
674 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
675 assert(MI.getOperand(OpNo).isReg());
676 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
677 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
679 return (OffBits & 0xFFFF) | RegBits;
682 unsigned MipsMCCodeEmitter::
683 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
684 SmallVectorImpl<MCFixup> &Fixups,
685 const MCSubtargetInfo &STI) const {
686 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
687 assert(MI.getOperand(OpNo).isReg());
688 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
690 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
693 return (OffBits & 0xF) | RegBits;
696 unsigned MipsMCCodeEmitter::
697 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
698 SmallVectorImpl<MCFixup> &Fixups,
699 const MCSubtargetInfo &STI) const {
700 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
701 assert(MI.getOperand(OpNo).isReg());
702 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
704 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
707 return (OffBits & 0xF) | RegBits;
710 unsigned MipsMCCodeEmitter::
711 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
712 SmallVectorImpl<MCFixup> &Fixups,
713 const MCSubtargetInfo &STI) const {
714 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
715 assert(MI.getOperand(OpNo).isReg());
716 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
718 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
721 return (OffBits & 0xF) | RegBits;
724 unsigned MipsMCCodeEmitter::
725 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
726 SmallVectorImpl<MCFixup> &Fixups,
727 const MCSubtargetInfo &STI) const {
728 // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
729 assert(MI.getOperand(OpNo).isReg() &&
730 MI.getOperand(OpNo).getReg() == Mips::SP &&
731 "Unexpected base register!");
732 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
735 return OffBits & 0x1F;
738 unsigned MipsMCCodeEmitter::
739 getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
740 SmallVectorImpl<MCFixup> &Fixups,
741 const MCSubtargetInfo &STI) const {
742 // Register is encoded in bits 9-7, offset is encoded in bits 6-0.
743 assert(MI.getOperand(OpNo).isReg() &&
744 MI.getOperand(OpNo).getReg() == Mips::GP &&
745 "Unexpected base register!");
747 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
750 return OffBits & 0x7F;
753 unsigned MipsMCCodeEmitter::
754 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
755 SmallVectorImpl<MCFixup> &Fixups,
756 const MCSubtargetInfo &STI) const {
757 // opNum can be invalid if instruction had reglist as operand.
758 // MemOperand is always last operand of instruction (base + offset).
759 switch (MI.getOpcode()) {
764 OpNo = MI.getNumOperands() - 2;
768 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
769 assert(MI.getOperand(OpNo).isReg());
770 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
771 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
773 return (OffBits & 0x0FFF) | RegBits;
776 unsigned MipsMCCodeEmitter::
777 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
778 SmallVectorImpl<MCFixup> &Fixups,
779 const MCSubtargetInfo &STI) const {
780 // opNum can be invalid if instruction had reglist as operand
781 // MemOperand is always last operand of instruction (base + offset)
782 switch (MI.getOpcode()) {
787 OpNo = MI.getNumOperands() - 2;
791 // Offset is encoded in bits 4-0.
792 assert(MI.getOperand(OpNo).isReg());
793 // Base register is always SP - thus it is not encoded.
794 assert(MI.getOperand(OpNo+1).isImm());
795 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
797 return ((OffBits >> 2) & 0x0F);
801 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
802 SmallVectorImpl<MCFixup> &Fixups,
803 const MCSubtargetInfo &STI) const {
804 assert(MI.getOperand(OpNo).isImm());
805 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
806 return SizeEncoding - 1;
809 // FIXME: should be called getMSBEncoding
812 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
813 SmallVectorImpl<MCFixup> &Fixups,
814 const MCSubtargetInfo &STI) const {
815 assert(MI.getOperand(OpNo-1).isImm());
816 assert(MI.getOperand(OpNo).isImm());
817 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
818 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
820 return Position + Size - 1;
824 MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
825 SmallVectorImpl<MCFixup> &Fixups,
826 const MCSubtargetInfo &STI) const {
827 assert(MI.getOperand(OpNo).isImm());
828 // The immediate is encoded as 'immediate - 1'.
829 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1;
833 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
834 SmallVectorImpl<MCFixup> &Fixups,
835 const MCSubtargetInfo &STI) const {
836 const MCOperand &MO = MI.getOperand(OpNo);
838 // The immediate is encoded as 'immediate << 2'.
839 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
840 assert((Res & 3) == 0);
844 assert(MO.isExpr() &&
845 "getSimm19Lsl2Encoding expects only expressions or an immediate");
847 const MCExpr *Expr = MO.getExpr();
848 Fixups.push_back(MCFixup::Create(0, Expr,
849 MCFixupKind(Mips::fixup_MIPS_PC19_S2)));
854 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
855 SmallVectorImpl<MCFixup> &Fixups,
856 const MCSubtargetInfo &STI) const {
857 const MCOperand &MO = MI.getOperand(OpNo);
859 // The immediate is encoded as 'immediate << 3'.
860 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
861 assert((Res & 7) == 0);
865 assert(MO.isExpr() &&
866 "getSimm18Lsl2Encoding expects only expressions or an immediate");
868 const MCExpr *Expr = MO.getExpr();
869 Fixups.push_back(MCFixup::Create(0, Expr,
870 MCFixupKind(Mips::fixup_MIPS_PC18_S3)));
875 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
876 SmallVectorImpl<MCFixup> &Fixups,
877 const MCSubtargetInfo &STI) const {
878 assert(MI.getOperand(OpNo).isImm());
879 const MCOperand &MO = MI.getOperand(OpNo);
880 return MO.getImm() % 8;
884 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
885 SmallVectorImpl<MCFixup> &Fixups,
886 const MCSubtargetInfo &STI) const {
887 assert(MI.getOperand(OpNo).isImm());
888 const MCOperand &MO = MI.getOperand(OpNo);
889 unsigned Value = MO.getImm();
891 case 128: return 0x0;
904 case 255: return 0xd;
905 case 32768: return 0xe;
906 case 65535: return 0xf;
908 llvm_unreachable("Unexpected value");
912 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
913 SmallVectorImpl<MCFixup> &Fixups,
914 const MCSubtargetInfo &STI) const {
917 // Register list operand is always first operand of instruction and it is
918 // placed before memory operand (register + imm).
920 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
921 unsigned Reg = MI.getOperand(I).getReg();
922 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
932 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
933 SmallVectorImpl<MCFixup> &Fixups,
934 const MCSubtargetInfo &STI) const {
935 return (MI.getNumOperands() - 4);
939 MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
940 SmallVectorImpl<MCFixup> &Fixups,
941 const MCSubtargetInfo &STI) const {
942 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
946 MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
947 SmallVectorImpl<MCFixup> &Fixups,
948 const MCSubtargetInfo &STI) const {
951 if (MI.getOperand(0).getReg() == Mips::A1 &&
952 MI.getOperand(1).getReg() == Mips::A2)
954 else if (MI.getOperand(0).getReg() == Mips::A1 &&
955 MI.getOperand(1).getReg() == Mips::A3)
957 else if (MI.getOperand(0).getReg() == Mips::A2 &&
958 MI.getOperand(1).getReg() == Mips::A3)
960 else if (MI.getOperand(0).getReg() == Mips::A0 &&
961 MI.getOperand(1).getReg() == Mips::S5)
963 else if (MI.getOperand(0).getReg() == Mips::A0 &&
964 MI.getOperand(1).getReg() == Mips::S6)
966 else if (MI.getOperand(0).getReg() == Mips::A0 &&
967 MI.getOperand(1).getReg() == Mips::A1)
969 else if (MI.getOperand(0).getReg() == Mips::A0 &&
970 MI.getOperand(1).getReg() == Mips::A2)
972 else if (MI.getOperand(0).getReg() == Mips::A0 &&
973 MI.getOperand(1).getReg() == Mips::A3)
980 MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
981 SmallVectorImpl<MCFixup> &Fixups,
982 const MCSubtargetInfo &STI) const {
983 const MCOperand &MO = MI.getOperand(OpNo);
984 assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate");
985 // The immediate is encoded as 'immediate >> 2'.
986 unsigned Res = static_cast<unsigned>(MO.getImm());
987 assert((Res & 3) == 0);
991 #include "MipsGenMCCodeEmitter.inc"