1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MCTargetDesc/MipsFixupKinds.h"
17 #include "MCTargetDesc/MipsMCTargetDesc.h"
18 #include "llvm/ADT/APFloat.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/Support/raw_ostream.h"
29 #define GET_INSTRMAP_INFO
30 #include "MipsGenInstrInfo.inc"
35 class MipsMCCodeEmitter : public MCCodeEmitter {
36 MipsMCCodeEmitter(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
37 void operator=(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
38 const MCInstrInfo &MCII;
40 const MCSubtargetInfo &STI;
44 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_,
45 const MCSubtargetInfo &sti, bool IsLittle) :
46 MCII(mcii), Ctx(Ctx_), STI (sti), IsLittleEndian(IsLittle) {}
48 ~MipsMCCodeEmitter() {}
50 void EmitByte(unsigned char C, raw_ostream &OS) const {
54 void EmitInstruction(uint64_t Val, unsigned Size, raw_ostream &OS) const {
55 // Output the instruction encoding in little endian byte order.
56 for (unsigned i = 0; i < Size; ++i) {
57 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
58 EmitByte((Val >> Shift) & 0xff, OS);
62 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
63 SmallVectorImpl<MCFixup> &Fixups) const;
65 // getBinaryCodeForInstr - TableGen'erated function for getting the
66 // binary encoding for an instruction.
67 uint64_t getBinaryCodeForInstr(const MCInst &MI,
68 SmallVectorImpl<MCFixup> &Fixups) const;
70 // getBranchJumpOpValue - Return binary encoding of the jump
71 // target operand. If the machine operand requires relocation,
72 // record the relocation and return zero.
73 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
74 SmallVectorImpl<MCFixup> &Fixups) const;
76 // getBranchTargetOpValue - Return binary encoding of the branch
77 // target operand. If the machine operand requires relocation,
78 // record the relocation and return zero.
79 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
80 SmallVectorImpl<MCFixup> &Fixups) const;
82 // getMachineOpValue - Return binary encoding of operand. If the machin
83 // operand requires relocation, record the relocation and return zero.
84 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
85 SmallVectorImpl<MCFixup> &Fixups) const;
87 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
88 SmallVectorImpl<MCFixup> &Fixups) const;
89 unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
90 SmallVectorImpl<MCFixup> &Fixups) const;
91 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
92 SmallVectorImpl<MCFixup> &Fixups) const;
95 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups) const;
97 }; // class MipsMCCodeEmitter
100 MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
101 const MCRegisterInfo &MRI,
102 const MCSubtargetInfo &STI,
105 return new MipsMCCodeEmitter(MCII, Ctx, STI, false);
108 MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
109 const MCRegisterInfo &MRI,
110 const MCSubtargetInfo &STI,
113 return new MipsMCCodeEmitter(MCII, Ctx, STI, true);
117 // If the D<shift> instruction has a shift amount that is greater
118 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
119 static void LowerLargeShift(MCInst& Inst) {
121 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
122 assert(Inst.getOperand(2).isImm());
124 int64_t Shift = Inst.getOperand(2).getImm();
126 return; // Do nothing
130 Inst.getOperand(2).setImm(Shift);
132 switch (Inst.getOpcode()) {
134 // Calling function is not synchronized
135 llvm_unreachable("Unexpected shift instruction");
137 Inst.setOpcode(Mips::DSLL32);
140 Inst.setOpcode(Mips::DSRL32);
143 Inst.setOpcode(Mips::DSRA32);
148 // Pick a DEXT or DINS instruction variant based on the pos and size operands
149 static void LowerDextDins(MCInst& InstIn) {
150 int Opcode = InstIn.getOpcode();
152 if (Opcode == Mips::DEXT)
153 assert(InstIn.getNumOperands() == 4 &&
154 "Invalid no. of machine operands for DEXT!");
155 else // Only DEXT and DINS are possible
156 assert(InstIn.getNumOperands() == 5 &&
157 "Invalid no. of machine operands for DINS!");
159 assert(InstIn.getOperand(2).isImm());
160 int64_t pos = InstIn.getOperand(2).getImm();
161 assert(InstIn.getOperand(3).isImm());
162 int64_t size = InstIn.getOperand(3).getImm();
165 if (pos < 32) // DEXT/DINS, do nothing
168 InstIn.getOperand(2).setImm(pos - 32);
169 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
173 assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
174 InstIn.getOperand(3).setImm(size - 32);
175 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
179 /// EncodeInstruction - Emit the instruction.
180 /// Size the instruction (currently only 4 bytes
181 void MipsMCCodeEmitter::
182 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
183 SmallVectorImpl<MCFixup> &Fixups) const
186 // Non-pseudo instructions that get changed for direct object
187 // only based on operand values.
188 // If this list of instructions get much longer we will move
189 // the check to a function call. Until then, this is more efficient.
191 switch (MI.getOpcode()) {
192 // If shift amount is >= 32 it the inst needs to be lowered further
196 LowerLargeShift(TmpInst);
198 // Double extract instruction is chosen by pos and size operands
201 LowerDextDins(TmpInst);
204 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups);
206 // Check for unimplemented opcodes.
207 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
208 // so we have to special check for them.
209 unsigned Opcode = TmpInst.getOpcode();
210 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
211 llvm_unreachable("unimplemented opcode in EncodeInstruction()");
213 if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
214 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
215 if (NewOpcode != -1) {
217 TmpInst.setOpcode (NewOpcode);
218 Binary = getBinaryCodeForInstr(TmpInst, Fixups);
222 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
224 // Get byte count of instruction
225 unsigned Size = Desc.getSize();
227 llvm_unreachable("Desc.getSize() returns 0");
229 EmitInstruction(Binary, Size, OS);
232 /// getBranchTargetOpValue - Return binary encoding of the branch
233 /// target operand. If the machine operand requires relocation,
234 /// record the relocation and return zero.
235 unsigned MipsMCCodeEmitter::
236 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
237 SmallVectorImpl<MCFixup> &Fixups) const {
239 const MCOperand &MO = MI.getOperand(OpNo);
241 // If the destination is an immediate, divide by 4.
242 if (MO.isImm()) return MO.getImm() >> 2;
244 assert(MO.isExpr() &&
245 "getBranchTargetOpValue expects only expressions or immediates");
247 const MCExpr *Expr = MO.getExpr();
248 Fixups.push_back(MCFixup::Create(0, Expr,
249 MCFixupKind(Mips::fixup_Mips_PC16)));
253 /// getJumpTargetOpValue - Return binary encoding of the jump
254 /// target operand. If the machine operand requires relocation,
255 /// record the relocation and return zero.
256 unsigned MipsMCCodeEmitter::
257 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
258 SmallVectorImpl<MCFixup> &Fixups) const {
260 const MCOperand &MO = MI.getOperand(OpNo);
261 // If the destination is an immediate, divide by 4.
262 if (MO.isImm()) return MO.getImm()>>2;
264 assert(MO.isExpr() &&
265 "getJumpTargetOpValue expects only expressions or an immediate");
267 const MCExpr *Expr = MO.getExpr();
268 Fixups.push_back(MCFixup::Create(0, Expr,
269 MCFixupKind(Mips::fixup_Mips_26)));
273 unsigned MipsMCCodeEmitter::
274 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups) const {
277 if (Expr->EvaluateAsAbsolute(Res))
280 MCExpr::ExprKind Kind = Expr->getKind();
281 if (Kind == MCExpr::Constant) {
282 return cast<MCConstantExpr>(Expr)->getValue();
285 if (Kind == MCExpr::Binary) {
286 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups);
287 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups);
290 if (Kind == MCExpr::SymbolRef) {
291 Mips::Fixups FixupKind = Mips::Fixups(0);
293 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
294 default: llvm_unreachable("Unknown fixup kind!");
296 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
297 FixupKind = Mips::fixup_Mips_GPOFF_HI;
299 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
300 FixupKind = Mips::fixup_Mips_GPOFF_LO;
302 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
303 FixupKind = Mips::fixup_Mips_GOT_PAGE;
305 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
306 FixupKind = Mips::fixup_Mips_GOT_OFST;
308 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
309 FixupKind = Mips::fixup_Mips_GOT_DISP;
311 case MCSymbolRefExpr::VK_Mips_GPREL:
312 FixupKind = Mips::fixup_Mips_GPREL16;
314 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
315 FixupKind = Mips::fixup_Mips_CALL16;
317 case MCSymbolRefExpr::VK_Mips_GOT16:
318 FixupKind = Mips::fixup_Mips_GOT_Global;
320 case MCSymbolRefExpr::VK_Mips_GOT:
321 FixupKind = Mips::fixup_Mips_GOT_Local;
323 case MCSymbolRefExpr::VK_Mips_ABS_HI:
324 FixupKind = Mips::fixup_Mips_HI16;
326 case MCSymbolRefExpr::VK_Mips_ABS_LO:
327 FixupKind = Mips::fixup_Mips_LO16;
329 case MCSymbolRefExpr::VK_Mips_TLSGD:
330 FixupKind = Mips::fixup_Mips_TLSGD;
332 case MCSymbolRefExpr::VK_Mips_TLSLDM:
333 FixupKind = Mips::fixup_Mips_TLSLDM;
335 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
336 FixupKind = Mips::fixup_Mips_DTPREL_HI;
338 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
339 FixupKind = Mips::fixup_Mips_DTPREL_LO;
341 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
342 FixupKind = Mips::fixup_Mips_GOTTPREL;
344 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
345 FixupKind = Mips::fixup_Mips_TPREL_HI;
347 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
348 FixupKind = Mips::fixup_Mips_TPREL_LO;
350 case MCSymbolRefExpr::VK_Mips_HIGHER:
351 FixupKind = Mips::fixup_Mips_HIGHER;
353 case MCSymbolRefExpr::VK_Mips_HIGHEST:
354 FixupKind = Mips::fixup_Mips_HIGHEST;
356 case MCSymbolRefExpr::VK_Mips_GOT_HI16:
357 FixupKind = Mips::fixup_Mips_GOT_HI16;
359 case MCSymbolRefExpr::VK_Mips_GOT_LO16:
360 FixupKind = Mips::fixup_Mips_GOT_LO16;
362 case MCSymbolRefExpr::VK_Mips_CALL_HI16:
363 FixupKind = Mips::fixup_Mips_CALL_HI16;
365 case MCSymbolRefExpr::VK_Mips_CALL_LO16:
366 FixupKind = Mips::fixup_Mips_CALL_LO16;
370 Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
376 /// getMachineOpValue - Return binary encoding of operand. If the machine
377 /// operand requires relocation, record the relocation and return zero.
378 unsigned MipsMCCodeEmitter::
379 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
380 SmallVectorImpl<MCFixup> &Fixups) const {
382 unsigned Reg = MO.getReg();
383 unsigned RegNo = Ctx.getRegisterInfo().getEncodingValue(Reg);
385 } else if (MO.isImm()) {
386 return static_cast<unsigned>(MO.getImm());
387 } else if (MO.isFPImm()) {
388 return static_cast<unsigned>(APFloat(MO.getFPImm())
389 .bitcastToAPInt().getHiBits(32).getLimitedValue());
391 // MO must be an Expr.
393 return getExprOpValue(MO.getExpr(),Fixups);
396 /// getMemEncoding - Return binary encoding of memory related operand.
397 /// If the offset operand requires relocation, record the relocation.
399 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
400 SmallVectorImpl<MCFixup> &Fixups) const {
401 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
402 assert(MI.getOperand(OpNo).isReg());
403 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
404 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
406 return (OffBits & 0xFFFF) | RegBits;
410 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
411 SmallVectorImpl<MCFixup> &Fixups) const {
412 assert(MI.getOperand(OpNo).isImm());
413 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
414 return SizeEncoding - 1;
417 // FIXME: should be called getMSBEncoding
420 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
421 SmallVectorImpl<MCFixup> &Fixups) const {
422 assert(MI.getOperand(OpNo-1).isImm());
423 assert(MI.getOperand(OpNo).isImm());
424 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
425 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
427 return Position + Size - 1;
430 #include "MipsGenMCCodeEmitter.inc"