1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MCTargetDesc/MipsFixupKinds.h"
17 #include "MCTargetDesc/MipsMCTargetDesc.h"
18 #include "llvm/ADT/APFloat.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/Support/raw_ostream.h"
29 #define GET_INSTRMAP_INFO
30 #include "MipsGenInstrInfo.inc"
35 class MipsMCCodeEmitter : public MCCodeEmitter {
36 MipsMCCodeEmitter(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
37 void operator=(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
38 const MCInstrInfo &MCII;
40 const MCSubtargetInfo &STI;
45 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_,
46 const MCSubtargetInfo &sti, bool IsLittle) :
47 MCII(mcii), Ctx(Ctx_), STI (sti), IsLittleEndian(IsLittle) {
48 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
51 ~MipsMCCodeEmitter() {}
53 void EmitByte(unsigned char C, raw_ostream &OS) const {
57 void EmitInstruction(uint64_t Val, unsigned Size, raw_ostream &OS) const {
58 // Output the instruction encoding in little endian byte order.
59 // Little-endian byte ordering:
60 // mips32r2: 4 | 3 | 2 | 1
61 // microMIPS: 2 | 1 | 4 | 3
62 if (IsLittleEndian && Size == 4 && IsMicroMips) {
63 EmitInstruction(Val>>16, 2, OS);
64 EmitInstruction(Val, 2, OS);
66 for (unsigned i = 0; i < Size; ++i) {
67 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
68 EmitByte((Val >> Shift) & 0xff, OS);
73 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
74 SmallVectorImpl<MCFixup> &Fixups) const;
76 // getBinaryCodeForInstr - TableGen'erated function for getting the
77 // binary encoding for an instruction.
78 uint64_t getBinaryCodeForInstr(const MCInst &MI,
79 SmallVectorImpl<MCFixup> &Fixups) const;
81 // getBranchJumpOpValue - Return binary encoding of the jump
82 // target operand. If the machine operand requires relocation,
83 // record the relocation and return zero.
84 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
85 SmallVectorImpl<MCFixup> &Fixups) const;
87 // getBranchJumpOpValueMM - Return binary encoding of the microMIPS jump
88 // target operand. If the machine operand requires relocation,
89 // record the relocation and return zero.
90 unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
91 SmallVectorImpl<MCFixup> &Fixups) const;
93 // getBranchTargetOpValue - Return binary encoding of the branch
94 // target operand. If the machine operand requires relocation,
95 // record the relocation and return zero.
96 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
97 SmallVectorImpl<MCFixup> &Fixups) const;
99 // getBranchTargetOpValue - Return binary encoding of the microMIPS branch
100 // target operand. If the machine operand requires relocation,
101 // record the relocation and return zero.
102 unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
103 SmallVectorImpl<MCFixup> &Fixups) const;
105 // getMachineOpValue - Return binary encoding of operand. If the machin
106 // operand requires relocation, record the relocation and return zero.
107 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
108 SmallVectorImpl<MCFixup> &Fixups) const;
110 unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
111 SmallVectorImpl<MCFixup> &Fixups) const;
113 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
114 SmallVectorImpl<MCFixup> &Fixups) const;
115 unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
116 SmallVectorImpl<MCFixup> &Fixups) const;
117 unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
118 SmallVectorImpl<MCFixup> &Fixups) const;
119 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
120 SmallVectorImpl<MCFixup> &Fixups) const;
122 // getLSAImmEncoding - Return binary encoding of LSA immediate.
123 unsigned getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
124 SmallVectorImpl<MCFixup> &Fixups) const;
127 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups) const;
129 }; // class MipsMCCodeEmitter
132 MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
133 const MCRegisterInfo &MRI,
134 const MCSubtargetInfo &STI,
137 return new MipsMCCodeEmitter(MCII, Ctx, STI, false);
140 MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
141 const MCRegisterInfo &MRI,
142 const MCSubtargetInfo &STI,
145 return new MipsMCCodeEmitter(MCII, Ctx, STI, true);
149 // If the D<shift> instruction has a shift amount that is greater
150 // than 31 (checked in calling routine), lower it to a D<shift>32 instruction
151 static void LowerLargeShift(MCInst& Inst) {
153 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
154 assert(Inst.getOperand(2).isImm());
156 int64_t Shift = Inst.getOperand(2).getImm();
158 return; // Do nothing
162 Inst.getOperand(2).setImm(Shift);
164 switch (Inst.getOpcode()) {
166 // Calling function is not synchronized
167 llvm_unreachable("Unexpected shift instruction");
169 Inst.setOpcode(Mips::DSLL32);
172 Inst.setOpcode(Mips::DSRL32);
175 Inst.setOpcode(Mips::DSRA32);
178 Inst.setOpcode(Mips::DROTR32);
183 // Pick a DEXT or DINS instruction variant based on the pos and size operands
184 static void LowerDextDins(MCInst& InstIn) {
185 int Opcode = InstIn.getOpcode();
187 if (Opcode == Mips::DEXT)
188 assert(InstIn.getNumOperands() == 4 &&
189 "Invalid no. of machine operands for DEXT!");
190 else // Only DEXT and DINS are possible
191 assert(InstIn.getNumOperands() == 5 &&
192 "Invalid no. of machine operands for DINS!");
194 assert(InstIn.getOperand(2).isImm());
195 int64_t pos = InstIn.getOperand(2).getImm();
196 assert(InstIn.getOperand(3).isImm());
197 int64_t size = InstIn.getOperand(3).getImm();
200 if (pos < 32) // DEXT/DINS, do nothing
203 InstIn.getOperand(2).setImm(pos - 32);
204 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
208 assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
209 InstIn.getOperand(3).setImm(size - 32);
210 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
214 /// EncodeInstruction - Emit the instruction.
215 /// Size the instruction with Desc.getSize().
216 void MipsMCCodeEmitter::
217 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
218 SmallVectorImpl<MCFixup> &Fixups) const
221 // Non-pseudo instructions that get changed for direct object
222 // only based on operand values.
223 // If this list of instructions get much longer we will move
224 // the check to a function call. Until then, this is more efficient.
226 switch (MI.getOpcode()) {
227 // If shift amount is >= 32 it the inst needs to be lowered further
232 LowerLargeShift(TmpInst);
234 // Double extract instruction is chosen by pos and size operands
237 LowerDextDins(TmpInst);
240 unsigned long N = Fixups.size();
241 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups);
243 // Check for unimplemented opcodes.
244 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
245 // so we have to special check for them.
246 unsigned Opcode = TmpInst.getOpcode();
247 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
248 llvm_unreachable("unimplemented opcode in EncodeInstruction()");
250 if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
251 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
252 if (NewOpcode != -1) {
253 if (Fixups.size() > N)
256 TmpInst.setOpcode (NewOpcode);
257 Binary = getBinaryCodeForInstr(TmpInst, Fixups);
261 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
263 // Get byte count of instruction
264 unsigned Size = Desc.getSize();
266 llvm_unreachable("Desc.getSize() returns 0");
268 EmitInstruction(Binary, Size, OS);
271 /// getBranchTargetOpValue - Return binary encoding of the branch
272 /// target operand. If the machine operand requires relocation,
273 /// record the relocation and return zero.
274 unsigned MipsMCCodeEmitter::
275 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
276 SmallVectorImpl<MCFixup> &Fixups) const {
278 const MCOperand &MO = MI.getOperand(OpNo);
280 // If the destination is an immediate, divide by 4.
281 if (MO.isImm()) return MO.getImm() >> 2;
283 assert(MO.isExpr() &&
284 "getBranchTargetOpValue expects only expressions or immediates");
286 const MCExpr *Expr = MO.getExpr();
287 Fixups.push_back(MCFixup::Create(0, Expr,
288 MCFixupKind(Mips::fixup_Mips_PC16)));
292 /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
293 /// target operand. If the machine operand requires relocation,
294 /// record the relocation and return zero.
295 unsigned MipsMCCodeEmitter::
296 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
297 SmallVectorImpl<MCFixup> &Fixups) const {
299 const MCOperand &MO = MI.getOperand(OpNo);
301 // If the destination is an immediate, divide by 2.
302 if (MO.isImm()) return MO.getImm() >> 1;
304 assert(MO.isExpr() &&
305 "getBranchTargetOpValueMM expects only expressions or immediates");
307 const MCExpr *Expr = MO.getExpr();
308 Fixups.push_back(MCFixup::Create(0, Expr,
310 fixup_MICROMIPS_PC16_S1)));
314 /// getJumpTargetOpValue - Return binary encoding of the jump
315 /// target operand. If the machine operand requires relocation,
316 /// record the relocation and return zero.
317 unsigned MipsMCCodeEmitter::
318 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
319 SmallVectorImpl<MCFixup> &Fixups) const {
321 const MCOperand &MO = MI.getOperand(OpNo);
322 // If the destination is an immediate, divide by 4.
323 if (MO.isImm()) return MO.getImm()>>2;
325 assert(MO.isExpr() &&
326 "getJumpTargetOpValue expects only expressions or an immediate");
328 const MCExpr *Expr = MO.getExpr();
329 Fixups.push_back(MCFixup::Create(0, Expr,
330 MCFixupKind(Mips::fixup_Mips_26)));
334 unsigned MipsMCCodeEmitter::
335 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
336 SmallVectorImpl<MCFixup> &Fixups) const {
338 const MCOperand &MO = MI.getOperand(OpNo);
339 // If the destination is an immediate, divide by 2.
340 if (MO.isImm()) return MO.getImm() >> 1;
342 assert(MO.isExpr() &&
343 "getJumpTargetOpValueMM expects only expressions or an immediate");
345 const MCExpr *Expr = MO.getExpr();
346 Fixups.push_back(MCFixup::Create(0, Expr,
347 MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
351 unsigned MipsMCCodeEmitter::
352 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups) const {
355 if (Expr->EvaluateAsAbsolute(Res))
358 MCExpr::ExprKind Kind = Expr->getKind();
359 if (Kind == MCExpr::Constant) {
360 return cast<MCConstantExpr>(Expr)->getValue();
363 if (Kind == MCExpr::Binary) {
364 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups);
365 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups);
368 if (Kind == MCExpr::SymbolRef) {
369 Mips::Fixups FixupKind = Mips::Fixups(0);
371 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
372 default: llvm_unreachable("Unknown fixup kind!");
374 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
375 FixupKind = Mips::fixup_Mips_GPOFF_HI;
377 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
378 FixupKind = Mips::fixup_Mips_GPOFF_LO;
380 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
381 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT_PAGE
382 : Mips::fixup_Mips_GOT_PAGE;
384 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
385 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT_OFST
386 : Mips::fixup_Mips_GOT_OFST;
388 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
389 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT_DISP
390 : Mips::fixup_Mips_GOT_DISP;
392 case MCSymbolRefExpr::VK_Mips_GPREL:
393 FixupKind = Mips::fixup_Mips_GPREL16;
395 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
396 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_CALL16
397 : Mips::fixup_Mips_CALL16;
399 case MCSymbolRefExpr::VK_Mips_GOT16:
400 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT16
401 : Mips::fixup_Mips_GOT_Global;
403 case MCSymbolRefExpr::VK_Mips_GOT:
404 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_GOT16
405 : Mips::fixup_Mips_GOT_Local;
407 case MCSymbolRefExpr::VK_Mips_ABS_HI:
408 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_HI16
409 : Mips::fixup_Mips_HI16;
411 case MCSymbolRefExpr::VK_Mips_ABS_LO:
412 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_LO16
413 : Mips::fixup_Mips_LO16;
415 case MCSymbolRefExpr::VK_Mips_TLSGD:
416 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_TLS_GD
417 : Mips::fixup_Mips_TLSGD;
419 case MCSymbolRefExpr::VK_Mips_TLSLDM:
420 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_TLS_LDM
421 : Mips::fixup_Mips_TLSLDM;
423 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
424 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
425 : Mips::fixup_Mips_DTPREL_HI;
427 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
428 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
429 : Mips::fixup_Mips_DTPREL_LO;
431 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
432 FixupKind = Mips::fixup_Mips_GOTTPREL;
434 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
435 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
436 : Mips::fixup_Mips_TPREL_HI;
438 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
439 FixupKind = IsMicroMips ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
440 : Mips::fixup_Mips_TPREL_LO;
442 case MCSymbolRefExpr::VK_Mips_HIGHER:
443 FixupKind = Mips::fixup_Mips_HIGHER;
445 case MCSymbolRefExpr::VK_Mips_HIGHEST:
446 FixupKind = Mips::fixup_Mips_HIGHEST;
448 case MCSymbolRefExpr::VK_Mips_GOT_HI16:
449 FixupKind = Mips::fixup_Mips_GOT_HI16;
451 case MCSymbolRefExpr::VK_Mips_GOT_LO16:
452 FixupKind = Mips::fixup_Mips_GOT_LO16;
454 case MCSymbolRefExpr::VK_Mips_CALL_HI16:
455 FixupKind = Mips::fixup_Mips_CALL_HI16;
457 case MCSymbolRefExpr::VK_Mips_CALL_LO16:
458 FixupKind = Mips::fixup_Mips_CALL_LO16;
462 Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
468 /// getMachineOpValue - Return binary encoding of operand. If the machine
469 /// operand requires relocation, record the relocation and return zero.
470 unsigned MipsMCCodeEmitter::
471 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
472 SmallVectorImpl<MCFixup> &Fixups) const {
474 unsigned Reg = MO.getReg();
475 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
477 } else if (MO.isImm()) {
478 return static_cast<unsigned>(MO.getImm());
479 } else if (MO.isFPImm()) {
480 return static_cast<unsigned>(APFloat(MO.getFPImm())
481 .bitcastToAPInt().getHiBits(32).getLimitedValue());
483 // MO must be an Expr.
485 return getExprOpValue(MO.getExpr(),Fixups);
488 /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
491 MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
492 SmallVectorImpl<MCFixup> &Fixups) const {
493 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
494 assert(MI.getOperand(OpNo).isReg());
495 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
496 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
498 // The immediate field of an LD/ST instruction is scaled which means it must
499 // be divided (when encoding) by the size (in bytes) of the instructions'
505 switch(MI.getOpcode())
508 assert (0 && "Unexpected instruction");
512 // We don't need to scale the offset in this case
528 return (OffBits & 0xFFFF) | RegBits;
531 /// getMemEncoding - Return binary encoding of memory related operand.
532 /// If the offset operand requires relocation, record the relocation.
534 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
535 SmallVectorImpl<MCFixup> &Fixups) const {
536 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
537 assert(MI.getOperand(OpNo).isReg());
538 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
539 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
541 return (OffBits & 0xFFFF) | RegBits;
544 unsigned MipsMCCodeEmitter::
545 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
546 SmallVectorImpl<MCFixup> &Fixups) const {
547 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
548 assert(MI.getOperand(OpNo).isReg());
549 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups) << 16;
550 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
552 return (OffBits & 0x0FFF) | RegBits;
556 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
557 SmallVectorImpl<MCFixup> &Fixups) const {
558 assert(MI.getOperand(OpNo).isImm());
559 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
560 return SizeEncoding - 1;
563 // FIXME: should be called getMSBEncoding
566 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
567 SmallVectorImpl<MCFixup> &Fixups) const {
568 assert(MI.getOperand(OpNo-1).isImm());
569 assert(MI.getOperand(OpNo).isImm());
570 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
571 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
573 return Position + Size - 1;
577 MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
578 SmallVectorImpl<MCFixup> &Fixups) const {
579 assert(MI.getOperand(OpNo).isImm());
580 // The immediate is encoded as 'immediate - 1'.
581 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups) - 1;
584 #include "MipsGenMCCodeEmitter.inc"