1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides Mips specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "MipsMCTargetDesc.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsMCAsmInfo.h"
17 #include "MipsTargetStreamer.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCELFStreamer.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/MC/MachineLocation.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/FormattedStream.h"
29 #include "llvm/Support/TargetRegistry.h"
31 #define GET_INSTRINFO_MC_DESC
32 #include "MipsGenInstrInfo.inc"
34 #define GET_SUBTARGETINFO_MC_DESC
35 #include "MipsGenSubtargetInfo.inc"
37 #define GET_REGINFO_MC_DESC
38 #include "MipsGenRegisterInfo.inc"
42 static std::string ParseMipsTriple(StringRef TT, StringRef CPU) {
43 std::string MipsArchFeature;
46 if (TheTriple.getArch() == Triple::mips ||
47 TheTriple.getArch() == Triple::mipsel) {
48 if (CPU.empty() || CPU == "mips32") {
49 MipsArchFeature = "+mips32";
50 } else if (CPU == "mips32r2") {
51 MipsArchFeature = "+mips32r2";
54 if (CPU.empty() || CPU == "mips64") {
55 MipsArchFeature = "+mips64";
56 } else if (CPU == "mips64r2") {
57 MipsArchFeature = "+mips64r2";
60 return MipsArchFeature;
63 static MCInstrInfo *createMipsMCInstrInfo() {
64 MCInstrInfo *X = new MCInstrInfo();
65 InitMipsMCInstrInfo(X);
69 static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) {
70 MCRegisterInfo *X = new MCRegisterInfo();
71 InitMipsMCRegisterInfo(X, Mips::RA);
75 static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
77 std::string ArchFS = ParseMipsTriple(TT,CPU);
80 ArchFS = ArchFS + "," + FS.str();
84 MCSubtargetInfo *X = new MCSubtargetInfo();
85 InitMipsMCSubtargetInfo(X, TT, CPU, ArchFS);
89 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
90 MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
92 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
93 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, SP, 0);
94 MAI->addInitialFrameState(Inst);
99 static MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM,
101 CodeGenOpt::Level OL) {
102 MCCodeGenInfo *X = new MCCodeGenInfo();
103 if (CM == CodeModel::JITDefault)
105 else if (RM == Reloc::Default)
107 X->InitMCCodeGenInfo(RM, CM, OL);
111 static MCInstPrinter *createMipsMCInstPrinter(const Target &T,
112 unsigned SyntaxVariant,
113 const MCAsmInfo &MAI,
114 const MCInstrInfo &MII,
115 const MCRegisterInfo &MRI,
116 const MCSubtargetInfo &STI) {
117 return new MipsInstPrinter(MAI, MII, MRI);
120 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
121 MCContext &Context, MCAsmBackend &MAB,
122 raw_ostream &OS, MCCodeEmitter *Emitter,
123 const MCSubtargetInfo &STI,
124 bool RelaxAll, bool NoExecStack) {
126 createELFStreamer(Context, MAB, OS, Emitter, RelaxAll, NoExecStack);
127 new MipsTargetELFStreamer(*S, STI);
132 createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
133 bool isVerboseAsm, bool useCFI, bool useDwarfDirectory,
134 MCInstPrinter *InstPrint, MCCodeEmitter *CE,
135 MCAsmBackend *TAB, bool ShowInst) {
137 llvm::createAsmStreamer(Ctx, OS, isVerboseAsm, useCFI, useDwarfDirectory,
138 InstPrint, CE, TAB, ShowInst);
139 new MipsTargetAsmStreamer(*S, OS);
143 extern "C" void LLVMInitializeMipsTargetMC() {
144 // Register the MC asm info.
145 RegisterMCAsmInfoFn X(TheMipsTarget, createMipsMCAsmInfo);
146 RegisterMCAsmInfoFn Y(TheMipselTarget, createMipsMCAsmInfo);
147 RegisterMCAsmInfoFn A(TheMips64Target, createMipsMCAsmInfo);
148 RegisterMCAsmInfoFn B(TheMips64elTarget, createMipsMCAsmInfo);
150 // Register the MC codegen info.
151 TargetRegistry::RegisterMCCodeGenInfo(TheMipsTarget,
152 createMipsMCCodeGenInfo);
153 TargetRegistry::RegisterMCCodeGenInfo(TheMipselTarget,
154 createMipsMCCodeGenInfo);
155 TargetRegistry::RegisterMCCodeGenInfo(TheMips64Target,
156 createMipsMCCodeGenInfo);
157 TargetRegistry::RegisterMCCodeGenInfo(TheMips64elTarget,
158 createMipsMCCodeGenInfo);
160 // Register the MC instruction info.
161 TargetRegistry::RegisterMCInstrInfo(TheMipsTarget, createMipsMCInstrInfo);
162 TargetRegistry::RegisterMCInstrInfo(TheMipselTarget, createMipsMCInstrInfo);
163 TargetRegistry::RegisterMCInstrInfo(TheMips64Target, createMipsMCInstrInfo);
164 TargetRegistry::RegisterMCInstrInfo(TheMips64elTarget,
165 createMipsMCInstrInfo);
167 // Register the MC register info.
168 TargetRegistry::RegisterMCRegInfo(TheMipsTarget, createMipsMCRegisterInfo);
169 TargetRegistry::RegisterMCRegInfo(TheMipselTarget, createMipsMCRegisterInfo);
170 TargetRegistry::RegisterMCRegInfo(TheMips64Target, createMipsMCRegisterInfo);
171 TargetRegistry::RegisterMCRegInfo(TheMips64elTarget,
172 createMipsMCRegisterInfo);
174 // Register the MC Code Emitter
175 TargetRegistry::RegisterMCCodeEmitter(TheMipsTarget,
176 createMipsMCCodeEmitterEB);
177 TargetRegistry::RegisterMCCodeEmitter(TheMipselTarget,
178 createMipsMCCodeEmitterEL);
179 TargetRegistry::RegisterMCCodeEmitter(TheMips64Target,
180 createMipsMCCodeEmitterEB);
181 TargetRegistry::RegisterMCCodeEmitter(TheMips64elTarget,
182 createMipsMCCodeEmitterEL);
184 // Register the object streamer.
185 TargetRegistry::RegisterMCObjectStreamer(TheMipsTarget, createMCStreamer);
186 TargetRegistry::RegisterMCObjectStreamer(TheMipselTarget, createMCStreamer);
187 TargetRegistry::RegisterMCObjectStreamer(TheMips64Target, createMCStreamer);
188 TargetRegistry::RegisterMCObjectStreamer(TheMips64elTarget,
191 // Register the asm streamer.
192 TargetRegistry::RegisterAsmStreamer(TheMipsTarget, createMCAsmStreamer);
193 TargetRegistry::RegisterAsmStreamer(TheMipselTarget, createMCAsmStreamer);
194 TargetRegistry::RegisterAsmStreamer(TheMips64Target, createMCAsmStreamer);
195 TargetRegistry::RegisterAsmStreamer(TheMips64elTarget, createMCAsmStreamer);
197 // Register the asm backend.
198 TargetRegistry::RegisterMCAsmBackend(TheMipsTarget,
199 createMipsAsmBackendEB32);
200 TargetRegistry::RegisterMCAsmBackend(TheMipselTarget,
201 createMipsAsmBackendEL32);
202 TargetRegistry::RegisterMCAsmBackend(TheMips64Target,
203 createMipsAsmBackendEB64);
204 TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget,
205 createMipsAsmBackendEL64);
207 // Register the MC subtarget info.
208 TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget,
209 createMipsMCSubtargetInfo);
210 TargetRegistry::RegisterMCSubtargetInfo(TheMipselTarget,
211 createMipsMCSubtargetInfo);
212 TargetRegistry::RegisterMCSubtargetInfo(TheMips64Target,
213 createMipsMCSubtargetInfo);
214 TargetRegistry::RegisterMCSubtargetInfo(TheMips64elTarget,
215 createMipsMCSubtargetInfo);
217 // Register the MCInstPrinter.
218 TargetRegistry::RegisterMCInstPrinter(TheMipsTarget,
219 createMipsMCInstPrinter);
220 TargetRegistry::RegisterMCInstPrinter(TheMipselTarget,
221 createMipsMCInstPrinter);
222 TargetRegistry::RegisterMCInstPrinter(TheMips64Target,
223 createMipsMCInstPrinter);
224 TargetRegistry::RegisterMCInstPrinter(TheMips64elTarget,
225 createMipsMCInstPrinter);