1 //===-- MipsOptionRecord.cpp - Abstraction for storing information --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MipsOptionRecord.h"
11 #include "MipsELFStreamer.h"
12 #include "llvm/MC/MCSectionELF.h"
16 void MipsRegInfoRecord::EmitMipsOptionRecord() {
17 MCAssembler &MCA = Streamer->getAssembler();
18 Triple T(STI.getTargetTriple());
19 uint64_t Features = STI.getFeatureBits();
21 Streamer->PushSection();
23 // We need to distinguish between N64 and the rest because at the moment
24 // we don't emit .Mips.options for other ELFs other than N64.
25 // Since .reginfo has the same information as .Mips.options (ODK_REGINFO),
26 // we can use the same abstraction (MipsRegInfoRecord class) to handle both.
27 if (Features & Mips::FeatureN64) {
28 // The EntrySize value of 1 seems strange since the records are neither
29 // 1-byte long nor fixed length but it matches the value GAS emits.
30 const MCSectionELF *Sec =
31 Context.getELFSection(".MIPS.options", ELF::SHT_MIPS_OPTIONS,
32 ELF::SHF_ALLOC | ELF::SHF_MIPS_NOSTRIP,
33 SectionKind::getMetadata(), 1, "");
34 MCA.getOrCreateSectionData(*Sec).setAlignment(8);
35 Streamer->SwitchSection(Sec);
37 Streamer->EmitIntValue(1, 1); // kind
38 Streamer->EmitIntValue(40, 1); // size
39 Streamer->EmitIntValue(0, 2); // section
40 Streamer->EmitIntValue(0, 4); // info
41 Streamer->EmitIntValue(ri_gprmask, 4);
42 Streamer->EmitIntValue(0, 4); // pad
43 Streamer->EmitIntValue(ri_cprmask[0], 4);
44 Streamer->EmitIntValue(ri_cprmask[1], 4);
45 Streamer->EmitIntValue(ri_cprmask[2], 4);
46 Streamer->EmitIntValue(ri_cprmask[3], 4);
47 Streamer->EmitIntValue(ri_gp_value, 8);
49 const MCSectionELF *Sec =
50 Context.getELFSection(".reginfo", ELF::SHT_MIPS_REGINFO, ELF::SHF_ALLOC,
51 SectionKind::getMetadata(), 24, "");
52 MCA.getOrCreateSectionData(*Sec)
53 .setAlignment(Features & Mips::FeatureN32 ? 8 : 4);
54 Streamer->SwitchSection(Sec);
56 Streamer->EmitIntValue(ri_gprmask, 4);
57 Streamer->EmitIntValue(ri_cprmask[0], 4);
58 Streamer->EmitIntValue(ri_cprmask[1], 4);
59 Streamer->EmitIntValue(ri_cprmask[2], 4);
60 Streamer->EmitIntValue(ri_cprmask[3], 4);
61 assert((ri_gp_value & 0xffffffff) == ri_gp_value);
62 Streamer->EmitIntValue(ri_gp_value, 4);
65 Streamer->PopSection();
68 void MipsRegInfoRecord::SetPhysRegUsed(unsigned Reg,
69 const MCRegisterInfo *MCRegInfo) {
72 for (MCSubRegIterator SubRegIt(Reg, MCRegInfo, true); SubRegIt.isValid();
74 unsigned CurrentSubReg = *SubRegIt;
76 unsigned EncVal = MCRegInfo->getEncodingValue(CurrentSubReg);
79 if (GPR32RegClass->contains(CurrentSubReg) ||
80 GPR64RegClass->contains(CurrentSubReg))
82 else if (FGR32RegClass->contains(CurrentSubReg) ||
83 FGR64RegClass->contains(CurrentSubReg) ||
84 AFGR64RegClass->contains(CurrentSubReg) ||
85 MSA128BRegClass->contains(CurrentSubReg))
86 ri_cprmask[1] |= Value;
87 else if (COP2RegClass->contains(CurrentSubReg))
88 ri_cprmask[2] |= Value;
89 else if (COP3RegClass->contains(CurrentSubReg))
90 ri_cprmask[3] |= Value;