1 //=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes microMIPS32r6 instruction formats.
12 //===----------------------------------------------------------------------===//
14 class MMR6Arch<string opstr> {
15 string Arch = "micromipsr6";
16 string BaseOpcode = opstr;
19 // Class used for microMIPS32r6 and microMIPS64r6 instructions.
20 class MicroMipsR6Inst16 : PredicateControl {
21 string DecoderNamespace = "MicroMipsR6";
22 let InsnPredicates = [HasMicroMips32r6];
25 class BC16_FM_MM16R6 {
30 let Inst{15-10} = 0x33;
31 let Inst{9-0} = offset;
34 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> : MicroMipsR6Inst16 {
42 let Inst{6-0} = offset;
45 class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst {
51 let Inst{31-26} = 0b000000;
54 let Inst{15-12} = 0b0000;
55 let Inst{11-6} = funct;
56 let Inst{5-0} = 0b111100;
59 class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst {
65 let Inst{31-26} = opgroup;
66 let Inst{25-21} = hint;
67 let Inst{20-16} = addr{20-16};
68 let Inst{15-12} = funct;
69 let Inst{11-0} = addr{11-0};
72 class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
84 let Inst{9-0} = funct;
87 class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
97 let Inst{15-0} = imm16;
100 class POOL32C_ST_EVA_FM_MMR6<bits<6> op, bits<3> funct> : MipsR6Inst {
103 bits<5> base = addr{20-16};
104 bits<9> offset = addr{8-0};
108 let Inst{31-26} = op;
109 let Inst{25-21} = hint;
110 let Inst{20-16} = base;
111 let Inst{15-12} = 0b1010;
112 let Inst{11-9} = funct;
113 let Inst{8-0} = offset;
116 class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
117 : MMR6Arch<instr_asm> {
123 let Inst{31-26} = 0b000000;
124 let Inst{25-21} = rd;
125 let Inst{20-16} = rt;
126 let Inst{15-6} = funct;
127 let Inst{5-0} = 0b111100;
130 class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
136 let Inst{31-26} = 0b011110;
137 let Inst{25-21} = rt;
138 let Inst{20-19} = funct;
139 let Inst{18-0} = imm;
142 class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst {
148 let Inst{31-26} = 0b011110;
149 let Inst{25-21} = rt;
150 let Inst{20-16} = funct;
151 let Inst{15-0} = imm;
154 class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
161 let Inst{31-26} = 0b000000;
162 let Inst{25-21} = rt;
163 let Inst{20-16} = rs;
164 let Inst{15-11} = rd;
166 let Inst{9-0} = funct;
169 class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {
175 let Inst{31-26} = 0b000000;
176 let Inst{25-21} = rt;
177 let Inst{20-16} = rs;
178 let Inst{15-6} = funct;
179 let Inst{5-0} = 0b111100;
182 class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst {
188 let Inst{31-26} = 0b000000;
189 let Inst{25-21} = rs;
190 let Inst{20-16} = 0b00000;
191 let Inst{15-11} = rt;
192 let Inst{10-6} = 0b00001;
193 let Inst{5-0} = funct;
196 class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst {
204 let Inst{31-26} = 0b000000;
205 let Inst{25-21} = rs;
206 let Inst{20-16} = rt;
207 let Inst{15-11} = rd;
209 let Inst{8-6} = 0b000;
210 let Inst{5-0} = funct;
213 class AUI_FM_MMR6 : MipsR6Inst {
220 let Inst{31-26} = 0b000100;
221 let Inst{25-21} = rt;
222 let Inst{20-16} = rs;
223 let Inst{15-0} = imm;
226 class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst {
234 let Inst{31-26} = 0b000000;
235 let Inst{25-21} = rt;
236 let Inst{20-16} = rs;
237 let Inst{15-11} = rd;
238 let Inst{10-9} = imm2;
239 let Inst{8-6} = 0b000;
240 let Inst{5-0} = funct;
243 class SB32_SH32_STORE_FM_MMR6<bits<6> op> {
246 bits<5> base = addr{20-16};
247 bits<16> offset = addr{15-0};
251 let Inst{31-26} = op;
252 let Inst{25-21} = rt;
253 let Inst{20-16} = base;
254 let Inst{15-0} = offset;
257 class POOL32C_STORE_EVA_FM_MMR6<bits<3> funct> {
260 bits<5> base = addr{20-16};
261 bits<9> offset = addr{8-0};
265 let Inst{31-26} = 0b011000;
266 let Inst{25-21} = rt;
267 let Inst{20-16} = base;
268 let Inst{15-12} = 0b1010;
269 let Inst{11-9} = funct;
270 let Inst{8-0} = offset;
273 class LOAD_WORD_EVA_FM_MMR6<bits<3> funct> {
276 bits<5> base = addr{20-16};
277 bits<9> offset = addr{8-0};
281 let Inst{31-26} = 0b011000;
282 let Inst{25-21} = rt;
283 let Inst{20-16} = base;
284 let Inst{15-12} = 0b0110;
285 let Inst{11-9} = funct;
286 let Inst{8-0} = offset;
289 class LOAD_WORD_FM_MMR6 {
292 bits<5> base = addr{20-16};
293 bits<16> offset = addr{15-0};
297 let Inst{31-26} = 0b111111;
298 let Inst{25-21} = rt;
299 let Inst{20-16} = base;
300 let Inst{15-0} = offset;
303 class LOAD_UPPER_IMM_FM_MMR6 {
309 let Inst{31-26} = 0b000100;
310 let Inst{25-21} = rt;
312 let Inst{15-0} = imm16;
315 class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
321 let Inst{31-26} = funct;
322 let Inst{25-21} = rt;
323 let Inst{20-16} = 0b00000;
324 let Inst{15-0} = offset;
327 class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
333 let Inst{31-26} = funct;
334 let Inst{25-21} = rt;
335 let Inst{20-16} = rt;
336 let Inst{15-0} = offset;
339 class ERET_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
342 let Inst{31-26} = 0x00;
343 let Inst{25-16} = 0x00;
344 let Inst{15-6} = 0x3cd;
345 let Inst{5-0} = 0x3c;
348 class ERETNC_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
351 let Inst{31-26} = 0x00;
352 let Inst{25-17} = 0x00;
353 let Inst{16-16} = 0x01;
354 let Inst{15-6} = 0x3cd;
355 let Inst{5-0} = 0x3c;
358 class BREAK_MMR6_ENC<string instr_asm> : MMR6Arch<instr_asm> {
362 let Inst{31-26} = 0x0;
363 let Inst{25-16} = code_1;
364 let Inst{15-6} = code_2;
365 let Inst{5-0} = 0x07;
368 class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
371 let Inst{31-26} = 0x0;
372 let Inst{25-21} = 0x0;
373 let Inst{20-16} = 0x0;
374 let Inst{15-11} = op;
375 let Inst{10-6} = 0x0;
379 class EIDI_MMR6_ENC<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
381 bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt
383 let Inst{31-26} = 0x00;
384 let Inst{25-21} = 0x00;
385 let Inst{20-16} = rt;
386 let Inst{15-6} = funct;
387 let Inst{5-0} = 0x3c;
390 class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> {
398 let Inst{25-21} = rd;
399 let Inst{20-16} = rt;
400 let Inst{15-11} = shamt;
401 let Inst{10} = rotate;
402 let Inst{9-0} = funct;
405 class SW32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
411 let Inst{31-26} = op;
412 let Inst{25-21} = rt;
413 let Inst{20-16} = addr{20-16};
414 let Inst{15-0} = addr{15-0};
417 class POOL32C_SWE_FM_MMR6<string instr_asm, bits<6> op, bits<4> fmt,
418 bits<3> funct> : MMR6Arch<instr_asm> {
421 bits<5> base = addr{20-16};
422 bits<9> offset = addr{8-0};
426 let Inst{31-26} = op;
427 let Inst{25-21} = rt;
428 let Inst{20-16} = base;
429 let Inst{15-12} = fmt;
430 let Inst{11-9} = funct;
431 let Inst{8-0} = offset;
434 class POOL32F_ARITH_FM_MMR6<string instr_asm, bits<2> fmt, bits<8> funct>
435 : MMR6Arch<instr_asm>, MipsR6Inst {
442 let Inst{31-26} = 0b010101;
443 let Inst{25-21} = ft;
444 let Inst{20-16} = fs;
445 let Inst{15-11} = fd;
448 let Inst{7-0} = funct;
451 class POOL32F_ARITHF_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
452 : MMR6Arch<instr_asm>, MipsR6Inst {
459 let Inst{31-26} = 0b010101;
460 let Inst{25-21} = ft;
461 let Inst{20-16} = fs;
462 let Inst{15-11} = fd;
463 let Inst{10-9} = fmt;
464 let Inst{8-0} = funct;
467 class POOL32F_MOV_NEG_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
468 : MMR6Arch<instr_asm>, MipsR6Inst {
474 let Inst{31-26} = 0b010101;
475 let Inst{25-21} = ft;
476 let Inst{20-16} = fs;
478 let Inst{14-13} = fmt;
479 let Inst{12-6} = funct;
480 let Inst{5-0} = 0b111011;
483 class POOL32F_MINMAX_FM<string instr_asm, bits<2> fmt, bits<9> funct>
484 : MMR6Arch<instr_asm>, MipsR6Inst {
491 let Inst{31-26} = 0b010101;
492 let Inst{25-21} = ft;
493 let Inst{20-16} = fs;
494 let Inst{15-11} = fd;
495 let Inst{10-9} = fmt;
496 let Inst{8-0} = funct;
499 class POOL32F_CMP_FM<string instr_asm, bits<6> format, FIELD_CMP_COND Cond>
500 : MMR6Arch<instr_asm>, MipsR6Inst {
507 let Inst{31-26} = 0b010101;
508 let Inst{25-21} = ft;
509 let Inst{20-16} = fs;
510 let Inst{15-11} = fd;
511 let Inst{10-6} = Cond.Value;
512 let Inst{5-0} = format;
515 class POOL32F_CVT_LW_FM<string instr_asm, bit fmt, bits<8> funct>
516 : MMR6Arch<instr_asm>, MipsR6Inst {
521 let Inst{31-26} = 0b010101;
522 let Inst{25-21} = ft;
523 let Inst{20-16} = fs;
526 let Inst{13-6} = funct;
527 let Inst{5-0} = 0b111011;
530 class POOL32F_CVT_DS_FM<string instr_asm, bits<2> fmt, bits<7> funct>
531 : MMR6Arch<instr_asm>, MipsR6Inst {
536 let Inst{31-26} = 0b010101;
537 let Inst{25-21} = ft;
538 let Inst{20-16} = fs;
540 let Inst{14-13} = fmt;
541 let Inst{12-6} = funct;
542 let Inst{5-0} = 0b111011;
545 class POOL32F_ABS_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
546 : MMR6Arch<instr_asm>, MipsR6Inst {
552 let Inst{31-26} = 0b010101;
553 let Inst{25-21} = ft;
554 let Inst{20-16} = fs;
556 let Inst{14-13} = fmt;
557 let Inst{12-6} = funct;
558 let Inst{5-0} = 0b111011;
561 class POOL32F_MATH_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
562 : MMR6Arch<instr_asm>, MipsR6Inst {
568 let Inst{31-26} = 0b010101;
569 let Inst{25-21} = ft;
570 let Inst{20-16} = fs;
573 let Inst{13-6} = funct;
574 let Inst{5-0} = 0b111011;
577 class POOL16A_ADDU16_FM_MMR6 : MicroMipsR6Inst16 {
584 let Inst{15-10} = 0b000001;
591 class POOL16C_AND16_FM_MMR6 : MicroMipsR6Inst16 {
597 let Inst{15-10} = 0b010001;
600 let Inst{3-0} = 0b0001;
603 class POOL16C_NOT16_FM_MMR6 : MicroMipsR6Inst16 {
609 let Inst{15-10} = 0x11;
612 let Inst{3-0} = 0b0000;
615 class POOL16C_OR16_FM_MMR6 : MicroMipsR6Inst16 {
621 let Inst{15-10} = 0b010001;
624 let Inst{3-0} = 0b1001;