1 //=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes microMIPS32r6 instruction formats.
12 //===----------------------------------------------------------------------===//
14 class MMR6Arch<string opstr> {
15 string Arch = "micromipsr6";
16 string BaseOpcode = opstr;
19 // Class used for microMIPS32r6 and microMIPS64r6 instructions.
20 class MicroMipsR6Inst16 : PredicateControl {
21 string DecoderNamespace = "MicroMipsR6";
22 let InsnPredicates = [HasMicroMips32r6];
25 class BC16_FM_MM16R6 {
30 let Inst{15-10} = 0x33;
31 let Inst{9-0} = offset;
34 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> : MicroMipsR6Inst16 {
42 let Inst{6-0} = offset;
45 class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
50 let Inst{15-10} = 0x11;
55 class POOL16C_JRCADDIUSP_FM_MM16R6<bits<5> op> {
60 let Inst{15-10} = 0x11;
65 class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst {
71 let Inst{31-26} = 0b000000;
74 let Inst{15-12} = 0b0000;
75 let Inst{11-6} = funct;
76 let Inst{5-0} = 0b111100;
79 class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst {
85 let Inst{31-26} = opgroup;
86 let Inst{25-21} = hint;
87 let Inst{20-16} = addr{20-16};
88 let Inst{15-12} = funct;
89 let Inst{11-0} = addr{11-0};
92 class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
100 let Inst{25-21} = rt;
101 let Inst{20-16} = rs;
102 let Inst{15-11} = rd;
104 let Inst{9-0} = funct;
107 class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
114 let Inst{31-26} = op;
115 let Inst{25-21} = rt;
116 let Inst{20-16} = rs;
117 let Inst{15-0} = imm16;
120 class POOL32C_ST_EVA_FM_MMR6<bits<6> op, bits<3> funct> : MipsR6Inst {
123 bits<5> base = addr{20-16};
124 bits<9> offset = addr{8-0};
128 let Inst{31-26} = op;
129 let Inst{25-21} = hint;
130 let Inst{20-16} = base;
131 let Inst{15-12} = 0b1010;
132 let Inst{11-9} = funct;
133 let Inst{8-0} = offset;
136 class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
137 : MMR6Arch<instr_asm> {
143 let Inst{31-26} = 0b000000;
144 let Inst{25-21} = rd;
145 let Inst{20-16} = rt;
146 let Inst{15-6} = funct;
147 let Inst{5-0} = 0b111100;
150 class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
156 let Inst{31-26} = 0b011110;
157 let Inst{25-21} = rt;
158 let Inst{20-19} = funct;
159 let Inst{18-0} = imm;
162 class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst {
168 let Inst{31-26} = 0b011110;
169 let Inst{25-21} = rt;
170 let Inst{20-16} = funct;
171 let Inst{15-0} = imm;
174 class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
181 let Inst{31-26} = 0b000000;
182 let Inst{25-21} = rt;
183 let Inst{20-16} = rs;
184 let Inst{15-11} = rd;
186 let Inst{9-0} = funct;
189 class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {
195 let Inst{31-26} = 0b000000;
196 let Inst{25-21} = rt;
197 let Inst{20-16} = rs;
198 let Inst{15-6} = funct;
199 let Inst{5-0} = 0b111100;
202 class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst {
208 let Inst{31-26} = 0b000000;
209 let Inst{25-21} = rs;
210 let Inst{20-16} = 0b00000;
211 let Inst{15-11} = rt;
212 let Inst{10-6} = 0b00001;
213 let Inst{5-0} = funct;
216 class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst {
224 let Inst{31-26} = 0b000000;
225 let Inst{25-21} = rs;
226 let Inst{20-16} = rt;
227 let Inst{15-11} = rd;
229 let Inst{8-6} = 0b000;
230 let Inst{5-0} = funct;
233 class AUI_FM_MMR6 : MipsR6Inst {
240 let Inst{31-26} = 0b000100;
241 let Inst{25-21} = rt;
242 let Inst{20-16} = rs;
243 let Inst{15-0} = imm;
246 class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst {
254 let Inst{31-26} = 0b000000;
255 let Inst{25-21} = rt;
256 let Inst{20-16} = rs;
257 let Inst{15-11} = rd;
258 let Inst{10-9} = imm2;
259 let Inst{8-6} = 0b000;
260 let Inst{5-0} = funct;
263 class SB32_SH32_STORE_FM_MMR6<bits<6> op> {
266 bits<5> base = addr{20-16};
267 bits<16> offset = addr{15-0};
271 let Inst{31-26} = op;
272 let Inst{25-21} = rt;
273 let Inst{20-16} = base;
274 let Inst{15-0} = offset;
277 class POOL32C_STORE_EVA_FM_MMR6<bits<3> funct> {
280 bits<5> base = addr{20-16};
281 bits<9> offset = addr{8-0};
285 let Inst{31-26} = 0b011000;
286 let Inst{25-21} = rt;
287 let Inst{20-16} = base;
288 let Inst{15-12} = 0b1010;
289 let Inst{11-9} = funct;
290 let Inst{8-0} = offset;
293 class LOAD_WORD_EVA_FM_MMR6<bits<3> funct> {
296 bits<5> base = addr{20-16};
297 bits<9> offset = addr{8-0};
301 let Inst{31-26} = 0b011000;
302 let Inst{25-21} = rt;
303 let Inst{20-16} = base;
304 let Inst{15-12} = 0b0110;
305 let Inst{11-9} = funct;
306 let Inst{8-0} = offset;
309 class LOAD_WORD_FM_MMR6 {
312 bits<5> base = addr{20-16};
313 bits<16> offset = addr{15-0};
317 let Inst{31-26} = 0b111111;
318 let Inst{25-21} = rt;
319 let Inst{20-16} = base;
320 let Inst{15-0} = offset;
323 class LOAD_UPPER_IMM_FM_MMR6 {
329 let Inst{31-26} = 0b000100;
330 let Inst{25-21} = rt;
332 let Inst{15-0} = imm16;
335 class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
341 let Inst{31-26} = funct;
342 let Inst{25-21} = rt;
343 let Inst{20-16} = 0b00000;
344 let Inst{15-0} = offset;
347 class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
353 let Inst{31-26} = funct;
354 let Inst{25-21} = rt;
355 let Inst{20-16} = rt;
356 let Inst{15-0} = offset;
359 class ERET_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
362 let Inst{31-26} = 0x00;
363 let Inst{25-16} = 0x00;
364 let Inst{15-6} = 0x3cd;
365 let Inst{5-0} = 0x3c;
368 class ERETNC_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
371 let Inst{31-26} = 0x00;
372 let Inst{25-17} = 0x00;
373 let Inst{16-16} = 0x01;
374 let Inst{15-6} = 0x3cd;
375 let Inst{5-0} = 0x3c;
378 class BREAK_MMR6_ENC<string instr_asm> : MMR6Arch<instr_asm> {
382 let Inst{31-26} = 0x0;
383 let Inst{25-16} = code_1;
384 let Inst{15-6} = code_2;
385 let Inst{5-0} = 0x07;
388 class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
391 let Inst{31-26} = 0x0;
392 let Inst{25-21} = 0x0;
393 let Inst{20-16} = 0x0;
394 let Inst{15-11} = op;
395 let Inst{10-6} = 0x0;
399 class EIDI_MMR6_ENC<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
401 bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt
403 let Inst{31-26} = 0x00;
404 let Inst{25-21} = 0x00;
405 let Inst{20-16} = rt;
406 let Inst{15-6} = funct;
407 let Inst{5-0} = 0x3c;
410 class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> {
418 let Inst{25-21} = rd;
419 let Inst{20-16} = rt;
420 let Inst{15-11} = shamt;
421 let Inst{10} = rotate;
422 let Inst{9-0} = funct;
425 class SW32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
431 let Inst{31-26} = op;
432 let Inst{25-21} = rt;
433 let Inst{20-16} = addr{20-16};
434 let Inst{15-0} = addr{15-0};
437 class POOL32C_SWE_FM_MMR6<string instr_asm, bits<6> op, bits<4> fmt,
438 bits<3> funct> : MMR6Arch<instr_asm> {
441 bits<5> base = addr{20-16};
442 bits<9> offset = addr{8-0};
446 let Inst{31-26} = op;
447 let Inst{25-21} = rt;
448 let Inst{20-16} = base;
449 let Inst{15-12} = fmt;
450 let Inst{11-9} = funct;
451 let Inst{8-0} = offset;
454 class POOL32F_ARITH_FM_MMR6<string instr_asm, bits<2> fmt, bits<8> funct>
455 : MMR6Arch<instr_asm>, MipsR6Inst {
462 let Inst{31-26} = 0b010101;
463 let Inst{25-21} = ft;
464 let Inst{20-16} = fs;
465 let Inst{15-11} = fd;
468 let Inst{7-0} = funct;
471 class POOL32F_ARITHF_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
472 : MMR6Arch<instr_asm>, MipsR6Inst {
479 let Inst{31-26} = 0b010101;
480 let Inst{25-21} = ft;
481 let Inst{20-16} = fs;
482 let Inst{15-11} = fd;
483 let Inst{10-9} = fmt;
484 let Inst{8-0} = funct;
487 class POOL32F_MOV_NEG_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
488 : MMR6Arch<instr_asm>, MipsR6Inst {
494 let Inst{31-26} = 0b010101;
495 let Inst{25-21} = ft;
496 let Inst{20-16} = fs;
498 let Inst{14-13} = fmt;
499 let Inst{12-6} = funct;
500 let Inst{5-0} = 0b111011;
503 class POOL32F_MINMAX_FM<string instr_asm, bits<2> fmt, bits<9> funct>
504 : MMR6Arch<instr_asm>, MipsR6Inst {
511 let Inst{31-26} = 0b010101;
512 let Inst{25-21} = ft;
513 let Inst{20-16} = fs;
514 let Inst{15-11} = fd;
515 let Inst{10-9} = fmt;
516 let Inst{8-0} = funct;
519 class POOL32F_CMP_FM<string instr_asm, bits<6> format, FIELD_CMP_COND Cond>
520 : MMR6Arch<instr_asm>, MipsR6Inst {
527 let Inst{31-26} = 0b010101;
528 let Inst{25-21} = ft;
529 let Inst{20-16} = fs;
530 let Inst{15-11} = fd;
531 let Inst{10-6} = Cond.Value;
532 let Inst{5-0} = format;
535 class POOL32F_CVT_LW_FM<string instr_asm, bit fmt, bits<8> funct>
536 : MMR6Arch<instr_asm>, MipsR6Inst {
541 let Inst{31-26} = 0b010101;
542 let Inst{25-21} = ft;
543 let Inst{20-16} = fs;
546 let Inst{13-6} = funct;
547 let Inst{5-0} = 0b111011;
550 class POOL32F_CVT_DS_FM<string instr_asm, bits<2> fmt, bits<7> funct>
551 : MMR6Arch<instr_asm>, MipsR6Inst {
556 let Inst{31-26} = 0b010101;
557 let Inst{25-21} = ft;
558 let Inst{20-16} = fs;
560 let Inst{14-13} = fmt;
561 let Inst{12-6} = funct;
562 let Inst{5-0} = 0b111011;
565 class POOL32F_ABS_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
566 : MMR6Arch<instr_asm>, MipsR6Inst {
572 let Inst{31-26} = 0b010101;
573 let Inst{25-21} = ft;
574 let Inst{20-16} = fs;
576 let Inst{14-13} = fmt;
577 let Inst{12-6} = funct;
578 let Inst{5-0} = 0b111011;
581 class POOL32F_MATH_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
582 : MMR6Arch<instr_asm>, MipsR6Inst {
588 let Inst{31-26} = 0b010101;
589 let Inst{25-21} = ft;
590 let Inst{20-16} = fs;
593 let Inst{13-6} = funct;
594 let Inst{5-0} = 0b111011;
597 class POOL16A_ADDU16_FM_MMR6 : MicroMipsR6Inst16 {
604 let Inst{15-10} = 0b000001;
611 class POOL16C_AND16_FM_MMR6 : MicroMipsR6Inst16 {
617 let Inst{15-10} = 0b010001;
620 let Inst{3-0} = 0b0001;
623 class POOL16C_NOT16_FM_MMR6 : MicroMipsR6Inst16 {
629 let Inst{15-10} = 0x11;
632 let Inst{3-0} = 0b0000;
635 class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> {
641 let Inst{15-10} = 0b010001;
647 class POOL16C_BREAKPOINT_FM_MMR6<bits<6> op> {
651 let Inst{15-10} = 0b010001;
652 let Inst{9-6} = code_;
656 class POOL16A_SUBU16_FM_MMR6 {
663 let Inst{15-10} = 0b000001;
670 class POOL32A_WRPGPR_WSBH_FM_MMR6<bits<10> funct> : MipsR6Inst {
676 let Inst{31-26} = 0x00;
677 let Inst{25-21} = rt;
678 let Inst{20-16} = rs;
679 let Inst{15-6} = funct;
680 let Inst{5-0} = 0x3c;