1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes microMIPSr6 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 // Instruction Encodings
18 //===----------------------------------------------------------------------===//
19 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
20 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
21 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
22 class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>;
23 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
24 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
25 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
26 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
27 class JIC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101000>;
28 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
29 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
30 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
31 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
32 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
33 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
34 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
36 //===----------------------------------------------------------------------===//
38 // Instruction Descriptions
40 //===----------------------------------------------------------------------===//
42 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
43 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
44 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
45 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
46 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
47 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
48 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
50 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
51 : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
52 dag InOperandList = (ins opnd:$offset);
53 dag OutOperandList = (outs);
54 string AsmString = !strconcat(instr_asm, "\t$offset");
58 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
60 list<Register> Defs = [RA];
62 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
63 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
64 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
66 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
67 : MMR6Arch<instr_asm> {
68 dag OutOperandList = (outs GPROpnd:$rd);
69 dag InOperandList = (ins GPROpnd:$rt);
70 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
71 list<dag> Pattern = [];
74 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
76 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
77 RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
78 dag OutOperandList = (outs);
79 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
80 string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
81 list<dag> Pattern = [];
82 string DecoderMethod = "DecodeCacheOpMM";
85 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
86 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
88 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
89 RegisterOperand GPROpnd>
91 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
92 string AsmString = !strconcat(opstr, "\t$rt, $offset");
93 list<dag> Pattern = [];
98 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
101 list<Register> Defs = [RA];
104 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
107 list<Register> Defs = [AT];
110 //===----------------------------------------------------------------------===//
112 // Instruction Definitions
114 //===----------------------------------------------------------------------===//
116 let DecoderNamespace = "MicroMips32r6" in {
117 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
118 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
119 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
120 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
121 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
122 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
124 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
125 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
126 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
127 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
128 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
129 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
130 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
131 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
132 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
133 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;