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[oota-llvm.git] / lib / Target / Mips / MicroMips32r6InstrInfo.td
1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes microMIPSr6 instructions.
11 //
12 //===----------------------------------------------------------------------===//
13
14 //===----------------------------------------------------------------------===//
15 //
16 // Instruction Encodings
17 //
18 //===----------------------------------------------------------------------===//
19 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
20 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
21 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
22 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
23 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
24 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
25 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
26 class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
27 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
28 class AUI_MMR6_ENC : AUI_FM_MMR6;
29 class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
30 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
31 class BC16_MMR6_ENC : BC16_FM_MM16R6;
32 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
33 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
34 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
35 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
36 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
37 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
38 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
39 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
40 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
41 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
42 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
43 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
44 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
45 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
46 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
47 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
48 class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>;
49 class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">;
50 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
51 class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
52 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
53 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
54 class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
55 class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
56 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
57 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
58 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
59 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
60 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
61 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
62 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
63 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
64 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
65 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
66 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
67 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
68 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
69 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
70 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
71 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
72 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
73 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
74 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
75 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
76 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
77 class PREFE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b010>;
78 class CACHEE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b011>;
79 class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x3c5>;
80 class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x1ec>;
81 class LB_MMR6_ENC : LB32_FM_MMR6;
82 class LBU_MMR6_ENC : LBU32_FM_MMR6;
83 class LBE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b100>;
84 class LBUE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b000>;
85 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
86 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
87 class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
88 class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
89 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
90 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
91 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
92 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
93 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
94 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
95 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
96 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
97 class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
98 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
99 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
100 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
101 class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
102 class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
103 class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
104 class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
105 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
106 class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
107 class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
108 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
109 class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
110 class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
111 class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
112 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
113 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
114
115 class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
116 class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
117 class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16;
118 class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
119 class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
120 class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
121 class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
122 class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
123 class LI16_MMR6_ENC : LI_FM_MM16;
124 class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
125 class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
126 class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
127 class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
128
129 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
130                                   RegisterOperand GPROpnd>
131     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
132   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
133   dag OutOperandList = (outs);
134   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
135   list<Register> Defs = [AT];
136 }
137
138 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
139                                                       GPR32Opnd> {
140   list<Register> Defs = [RA];
141 }
142
143 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
144                                                       GPR32Opnd> {
145   list<Register> Defs = [RA];
146 }
147
148 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
149                                                       GPR32Opnd> {
150   list<Register> Defs = [RA];
151 }
152
153 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
154                                                       GPR32Opnd> {
155   list<Register> Defs = [RA];
156 }
157
158 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
159                                                       GPR32Opnd> {
160   list<Register> Defs = [RA];
161 }
162
163 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
164                                                       GPR32Opnd> {
165   list<Register> Defs = [RA];
166 }
167
168 /// Floating Point Instructions
169 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
170 class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
171 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
172 class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
173 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
174 class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
175 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
176 class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
177 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
178 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
179 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
180 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
181 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
182 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
183 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
184 class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
185 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
186 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
187 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
188 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
189 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
190 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
191 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
192 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
193
194 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
195 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
196 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
197 class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
198 class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
199 class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
200 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
201 class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
202 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
203 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
204
205 //===----------------------------------------------------------------------===//
206 //
207 // Instruction Descriptions
208 //
209 //===----------------------------------------------------------------------===//
210
211 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
212 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
213 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
214 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
215 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
216 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
217 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
218
219 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
220     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
221   dag InOperandList = (ins opnd:$offset);
222   dag OutOperandList = (outs);
223   string AsmString = !strconcat(instr_asm, "\t$offset");
224   bit isBarrier = 1;
225 }
226
227 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
228   bit isCall = 1;
229   list<Register> Defs = [RA];
230 }
231 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
232
233 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
234                                        !strconcat("bc16", "\t$offset"), [],
235                                        II_BC, FrmI>,
236                        MMR6Arch<"bc16">, MicroMipsR6Inst16 {
237   let isBranch = 1;
238   let isTerminator = 1;
239   let isBarrier = 1;
240   let hasDelaySlot = 0;
241   let AdditionalPredicates = [RelocPIC];
242   let Defs = [AT];
243 }
244
245 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
246     : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>, MMR6Arch<instr_asm> {
247   let isBranch = 1;
248   let isTerminator = 1;
249   let hasDelaySlot = 0;
250   let Defs = [AT];
251 }
252 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
253 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
254
255 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
256 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
257
258 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
259     : MMR6Arch<instr_asm> {
260   dag OutOperandList = (outs GPROpnd:$rd);
261   dag InOperandList = (ins GPROpnd:$rt);
262   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
263   list<dag> Pattern = [];
264 }
265
266 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
267
268 class BRK_MMR6_DESC : BRK_FT<"break">;
269
270 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
271                            RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
272   dag OutOperandList = (outs);
273   dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
274   string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
275   list<dag> Pattern = [];
276   string DecoderMethod = "DecodeCacheOpMM";
277 }
278
279 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
280 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
281
282 class PREFE_CACHEE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
283                                   RegisterOperand GPROpnd> :
284                                   CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd,
285                                   GPROpnd> {
286   string DecoderMethod = "DecodePrefeOpMM";
287 }
288
289 class PREFE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"prefe", mem_mm_9, GPR32Opnd>;
290 class CACHEE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"cachee", mem_mm_9, GPR32Opnd>;
291
292 class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
293                             RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
294   dag OutOperandList = (outs GPROpnd:$rt);
295   dag InOperandList = (ins MemOpnd:$addr);
296   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
297   string DecoderMethod = "DecodeLoadByte15";
298   bit mayLoad = 1;
299 }
300 class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd>;
301 class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd>;
302
303 class LBE_LBUE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
304                               RegisterOperand GPROpnd>
305     : LB_LBU_MMR6_DESC_BASE<instr_asm, MemOpnd, GPROpnd> {
306   let DecoderMethod = "DecodeLoadByte9";
307 }
308 class LBE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbe", mem_mm_9, GPR32Opnd>;
309 class LBUE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbue", mem_mm_9, GPR32Opnd>;
310
311 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
312     : MMR6Arch<instr_asm> {
313   dag OutOperandList = (outs GPROpnd:$rt);
314   dag InOperandList = (ins GPROpnd:$rs);
315   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
316 }
317
318 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
319 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
320
321 class EHB_MMR6_DESC : Barrier<"ehb">;
322 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
323
324 class ERET_MMR6_DESC : ER_FT<"eret">;
325 class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
326
327 class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
328     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
329                       [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
330       MMR6Arch<opstr>, MicroMipsR6Inst16 {
331   let isCall = 1;
332   let hasDelaySlot = 0;
333   let Defs = [RA];
334 }
335 class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
336
337 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
338                                      RegisterOperand GPROpnd>
339     : MMR6Arch<opstr> {
340   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
341   string AsmString = !strconcat(opstr, "\t$rt, $offset");
342   list<dag> Pattern = [];
343   bit isTerminator = 1;
344   bit hasDelaySlot = 0;
345 }
346
347 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
348                                                        GPR32Opnd> {
349   bit isCall = 1;
350   list<Register> Defs = [RA];
351 }
352
353 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
354                                                      GPR32Opnd> {
355   bit isBarrier = 1;
356   list<Register> Defs = [AT];
357 }
358
359 class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
360     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
361                       [], II_JR, FrmR>,
362       MMR6Arch<opstr>, MicroMipsR6Inst16 {
363   let hasDelaySlot = 0;
364   let isBranch = 1;
365   let isIndirectBranch = 1;
366 }
367 class JRC16_MMR6_DESC : JRC16_MMR6_DESC_BASE<"jrc16", GPR32Opnd>;
368
369 class JRCADDIUSP_MMR6_DESC
370     : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm",
371                       [], II_JRADDIUSP, FrmR>,
372       MMR6Arch<"jrcaddiusp">, MicroMipsR6Inst16 {
373   let hasDelaySlot = 0;
374   let isTerminator = 1;
375   let isBarrier = 1;
376   let isBranch = 1;
377   let isIndirectBranch = 1;
378 }
379
380 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
381                       Operand ImmOpnd>  : MMR6Arch<instr_asm> {
382   dag OutOperandList = (outs GPROpnd:$rd);
383   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
384   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
385   list<dag> Pattern = [];
386 }
387
388 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
389
390 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
391     : MMR6Arch<instr_asm> {
392   dag OutOperandList = (outs GPROpnd:$rt);
393   dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
394   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
395   list<dag> Pattern = [];
396 }
397
398 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
399
400 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
401 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
402 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
403     : MMR6Arch<instr_asm> {
404   dag OutOperandList = (outs GPROpnd:$rt);
405   dag InOperandList = (ins simm16:$imm);
406   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
407   list<dag> Pattern = [];
408 }
409
410 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
411 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
412
413 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
414                          Operand ImmOpnd> : MMR6Arch<instr_asm> {
415   dag OutOperandList = (outs GPROpnd:$rd);
416   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
417   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
418   list<dag> Pattern = [];
419 }
420
421 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2>;
422
423 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
424                            Operand ImmOpnd> : MMR6Arch<instr_asm> {
425   dag OutOperandList = (outs GPROpnd:$rt);
426   dag InOperandList = (ins ImmOpnd:$imm);
427   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
428   list<dag> Pattern = [];
429 }
430
431 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
432 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
433
434 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
435     : MMR6Arch<instr_asm> {
436   dag OutOperandList = (outs GPROpnd:$rd);
437   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
438   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
439   list<dag> Pattern = [];
440 }
441
442 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
443 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
444 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
445 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
446 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
447 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
448 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
449 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
450 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
451 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
452 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
453 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
454 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
455 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
456
457 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
458                   SDPatternOperator OpNode = null_frag,
459                   InstrItinClass Itin = NoItinerary,
460                   ComplexPattern Addr = addr> :
461   InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
462          [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
463   let DecoderMethod = "DecodeMem";
464   let mayStore = 1;
465 }
466 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
467 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9>;
468
469 class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
470     : MMR6Arch<instr_asm> {
471   dag InOperandList = (ins RO:$rs);
472   dag OutOperandList = (outs RO:$rt);
473   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
474   list<dag> Pattern = [];
475   Format f = FrmR;
476   string BaseOpcode = instr_asm;
477   bit hasSideEffects = 0;
478 }
479 class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd>;
480 class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd>;
481
482 /// Floating Point Instructions
483 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
484                             InstrItinClass Itin, bit isComm,
485                             SDPatternOperator OpNode = null_frag> : HARDFLOAT {
486   dag OutOperandList = (outs RC:$fd);
487   dag InOperandList = (ins RC:$ft, RC:$fs);
488   string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
489   list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
490   InstrItinClass Itinerary = Itin;
491   bit isCommutable = isComm;
492 }
493 class FADD_S_MMR6_DESC
494   : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
495 class FADD_D_MMR6_DESC
496   : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
497 class FSUB_S_MMR6_DESC
498   : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
499 class FSUB_D_MMR6_DESC
500   : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
501 class FMUL_S_MMR6_DESC
502   : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
503 class FMUL_D_MMR6_DESC
504   : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
505 class FDIV_S_MMR6_DESC
506   : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
507 class FDIV_D_MMR6_DESC
508   : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
509 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
510 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
511 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
512 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
513
514 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
515                                RegisterOperand SrcRC, InstrItinClass Itin,
516                                SDPatternOperator OpNode = null_frag>
517                                : HARDFLOAT, NeverHasSideEffects {
518   dag OutOperandList = (outs DstRC:$ft);
519   dag InOperandList = (ins SrcRC:$fs);
520   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
521   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
522   InstrItinClass Itinerary = Itin;
523   Format Form = FrmFR;
524 }
525 class FMOV_S_MMR6_DESC
526   : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
527 class FMOV_D_MMR6_DESC
528   : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
529 class FNEG_S_MMR6_DESC
530   : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
531 class FNEG_D_MMR6_DESC
532   : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
533
534 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT;
535 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT;
536 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT;
537 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT;
538
539 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT;
540 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT;
541 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT;
542 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT;
543
544 class CVT_MMR6_DESC_BASE<
545     string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
546     InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
547     : HARDFLOAT, NeverHasSideEffects {
548   dag OutOperandList = (outs DstRC:$ft);
549   dag InOperandList = (ins SrcRC:$fs);
550   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
551   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
552   InstrItinClass Itinerary = Itin;
553   Format Form = FrmFR;
554 }
555
556 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
557                                              II_CVT>;
558 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
559                                              II_CVT>;
560 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
561                                              II_CVT>;
562 class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
563                                              II_CVT>;
564 class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
565                                              II_CVT>;
566 class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
567                                              II_CVT>;
568 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
569                                              II_CVT>, FGR_64;
570 class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
571                                              II_CVT>;
572 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
573                                              II_CVT>;
574 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
575                                              II_CVT>, FGR_64;
576
577 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
578                        RegisterOperand FGROpnd> {
579   def CMP_AF_#NAME : POOL32F_CMP_FM<
580       !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
581       CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
582       ISA_MICROMIPS32R6;
583   def CMP_UN_#NAME : POOL32F_CMP_FM<
584       !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
585       CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
586       ISA_MICROMIPS32R6;
587   def CMP_EQ_#NAME : POOL32F_CMP_FM<
588       !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
589       CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
590       ISA_MICROMIPS32R6;
591   def CMP_UEQ_#NAME : POOL32F_CMP_FM<
592       !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
593       CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
594       ISA_MICROMIPS32R6;
595   def CMP_LT_#NAME : POOL32F_CMP_FM<
596       !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
597       CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
598       ISA_MICROMIPS32R6;
599   def CMP_ULT_#NAME : POOL32F_CMP_FM<
600       !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
601       CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
602       ISA_MICROMIPS32R6;
603   def CMP_LE_#NAME : POOL32F_CMP_FM<
604       !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
605       CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
606       ISA_MICROMIPS32R6;
607   def CMP_ULE_#NAME : POOL32F_CMP_FM<
608       !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
609       CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
610       ISA_MICROMIPS32R6;
611   def CMP_SAF_#NAME : POOL32F_CMP_FM<
612       !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
613       CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
614       ISA_MICROMIPS32R6;
615   def CMP_SUN_#NAME : POOL32F_CMP_FM<
616       !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
617       CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
618       ISA_MICROMIPS32R6;
619   def CMP_SEQ_#NAME : POOL32F_CMP_FM<
620       !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
621       CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
622       ISA_MICROMIPS32R6;
623   def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
624       !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
625       CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
626       ISA_MICROMIPS32R6;
627   def CMP_SLT_#NAME : POOL32F_CMP_FM<
628       !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
629       CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
630       ISA_MICROMIPS32R6;
631   def CMP_SULT_#NAME : POOL32F_CMP_FM<
632       !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
633       CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
634       ISA_MICROMIPS32R6;
635   def CMP_SLE_#NAME : POOL32F_CMP_FM<
636       !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
637       CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
638       ISA_MICROMIPS32R6;
639   def CMP_SULE_#NAME : POOL32F_CMP_FM<
640       !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
641       CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
642       ISA_MICROMIPS32R6;
643 }
644
645 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
646                              RegisterOperand SrcRC, InstrItinClass Itin,
647                              SDPatternOperator OpNode = null_frag>
648     : HARDFLOAT, NeverHasSideEffects {
649   dag OutOperandList = (outs DstRC:$ft);
650   dag InOperandList  = (ins SrcRC:$fs);
651   string AsmString   = !strconcat(instr_asm, "\t$ft, $fs");
652   list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
653   InstrItinClass Itinerary = Itin;
654   Format Form = FrmFR;
655   list<Predicate> EncodingPredicates = [HasStdEnc];
656 }
657
658 class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd,
659                                                 II_ABS, fabs>;
660 class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd,
661                                                 II_ABS, fabs>;
662 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
663                                                     FGR32Opnd, II_FLOOR>;
664 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
665                                                     FGR64Opnd, II_FLOOR>;
666 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
667                                                     FGR32Opnd, II_FLOOR>;
668 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
669                                                     AFGR64Opnd, II_FLOOR>;
670 class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
671                                                    FGR32Opnd, II_CEIL>;
672 class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
673                                                    FGR64Opnd, II_CEIL>;
674 class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
675                                                    FGR32Opnd, II_CEIL>;
676 class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
677                                                    AFGR64Opnd, II_CEIL>;
678 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
679                                                     FGR32Opnd, II_TRUNC>;
680 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
681                                                     FGR64Opnd, II_TRUNC>;
682 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
683                                                     FGR32Opnd, II_TRUNC>;
684 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
685                                                     AFGR64Opnd, II_TRUNC>;
686 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
687                                                  II_SQRT_S, fsqrt>;
688 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
689                                                  II_SQRT_D, fsqrt>;
690 class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
691                                                   FGR32Opnd, II_TRUNC>;
692 class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
693                                                   AFGR64Opnd, II_TRUNC>;
694
695 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO>
696     : Store<opstr, RO>, MMR6Arch<opstr> {
697   let DecoderMethod = "DecodeMemMMImm16";
698 }
699 class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>;
700
701 class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
702     : MMR6Arch<instr_asm>, MipsR6Inst {
703   dag OutOperandList = (outs);
704   dag InOperandList = (ins RO:$rt, mem_mm_9:$addr);
705   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
706   string DecoderMethod = "DecodeStoreEvaOpMM";
707   bit mayStore = 1;
708 }
709 class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd>;
710 class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>;
711 class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>;
712 class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>;
713 class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
714             MMR6Arch<instr_asm>, MipsR6Inst {
715   dag OutOperandList = (outs RO:$rt);
716   dag InOperandList = (ins mem_mm_12:$addr);
717   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
718   string DecoderMethod = "DecodeMemMMImm9";
719   bit mayLoad = 1;
720 }
721 class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
722 class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
723 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
724       MMR6Arch<"addu16">;
725 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
726       MMR6Arch<"and16">;
727 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
728       MMR6Arch<"andi16">;
729 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">;
730 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
731       MMR6Arch<"or16">;
732 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
733       MMR6Arch<"sll16">;
734 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
735       MMR6Arch<"srl16">;
736 class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"srl16">,
737       MicroMipsR6Inst16;
738 class LI16_MMR6_DESC : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>,
739       MMR6Arch<"srl16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
740 class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"srl16">,
741       MicroMipsR6Inst16;
742 class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">,
743       MicroMipsR6Inst16;
744 class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
745       MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
746 class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
747       MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
748
749 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
750   dag OutOperandList = (outs GPR32Opnd:$rt);
751   dag InOperandList = (ins mem:$addr);
752   string AsmString = "lw\t$rt, $addr";
753   let DecoderMethod = "DecodeMemMMImm16";
754   let canFoldAsLoad = 1;
755   let mayLoad = 1;
756   list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
757   InstrItinClass Itinerary = II_LW;
758 }
759
760 class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
761   dag OutOperandList = (outs GPR32Opnd:$rt);
762   dag InOperandList = (ins uimm16:$imm16);
763   string AsmString = "lui\t$rt, $imm16";
764   list<dag> Pattern = [];
765   bit hasSideEffects = 0;
766   bit isReMaterializable = 1;
767   InstrItinClass Itinerary = II_LUI;
768   Format Form = FrmI;
769 }
770
771 //===----------------------------------------------------------------------===//
772 //
773 // Instruction Definitions
774 //
775 //===----------------------------------------------------------------------===//
776
777 let DecoderNamespace = "MicroMipsR6" in {
778 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
779 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
780 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
781 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
782                    ISA_MICROMIPS32R6;
783 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
784                   ISA_MICROMIPS32R6;
785 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
786 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
787 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
788 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
789 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
790 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
791 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
792 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
793 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
794                    ISA_MICROMIPS32R6;
795 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
796                    ISA_MICROMIPS32R6;
797 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
798                    ISA_MICROMIPS32R6;
799 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
800                    ISA_MICROMIPS32R6;
801 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
802                    ISA_MICROMIPS32R6;
803 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
804                    ISA_MICROMIPS32R6;
805 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
806                    ISA_MICROMIPS32R6;
807 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
808                    ISA_MICROMIPS32R6;
809 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
810                    ISA_MICROMIPS32R6;
811 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
812 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
813 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
814 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
815 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
816 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
817 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
818 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
819 def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
820 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
821                   ISA_MICROMIPS32R6;
822 def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
823                    ISA_MICROMIPS32R6;
824 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
825 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
826 def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
827 def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
828                       ISA_MICROMIPS32R6;
829 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
830 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
831 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
832 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
833 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
834 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
835 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
836 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
837 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
838 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
839 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
840 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
841 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
842 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
843 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
844                   ISA_MICROMIPS32R6;
845 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
846                   ISA_MICROMIPS32R6;
847 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
848 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
849 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
850 def PREFE_MMR6 : StdMMR6Rel, PREFE_MMR6_ENC, PREFE_MMR6_DESC, ISA_MICROMIPS32R6;
851 def CACHEE_MMR6 : StdMMR6Rel, CACHEE_MMR6_ENC, CACHEE_MMR6_DESC,
852                   ISA_MICROMIPS32R6;
853 def WRPGPR_MMR6 : StdMMR6Rel, WRPGPR_MMR6_ENC, WRPGPR_MMR6_DESC,
854                   ISA_MICROMIPS32R6;
855 def WSBH_MMR6 : StdMMR6Rel, WSBH_MMR6_ENC, WSBH_MMR6_DESC, ISA_MICROMIPS32R6;
856 def LB_MMR6 : R6MMR6Rel, LB_MMR6_ENC, LB_MMR6_DESC, ISA_MICROMIPS32R6;
857 def LBU_MMR6 : R6MMR6Rel, LBU_MMR6_ENC, LBU_MMR6_DESC, ISA_MICROMIPS32R6;
858 def LBE_MMR6 : R6MMR6Rel, LBE_MMR6_ENC, LBE_MMR6_DESC, ISA_MICROMIPS32R6;
859 def LBUE_MMR6 : R6MMR6Rel, LBUE_MMR6_ENC, LBUE_MMR6_DESC, ISA_MICROMIPS32R6;
860 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
861 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
862 let DecoderMethod = "DecodeMemMMImm16" in {
863   def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
864 }
865 let DecoderMethod = "DecodeMemMMImm9" in {
866   def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
867 }
868 /// Floating Point Instructions
869 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
870                   ISA_MICROMIPS32R6;
871 def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
872                   ISA_MICROMIPS32R6;
873 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
874                   ISA_MICROMIPS32R6;
875 def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
876                   ISA_MICROMIPS32R6;
877 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
878                   ISA_MICROMIPS32R6;
879 def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
880                   ISA_MICROMIPS32R6;
881 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
882                   ISA_MICROMIPS32R6;
883 def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
884                   ISA_MICROMIPS32R6;
885 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
886                    ISA_MICROMIPS32R6;
887 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
888                    ISA_MICROMIPS32R6;
889 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
890                    ISA_MICROMIPS32R6;
891 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
892                    ISA_MICROMIPS32R6;
893 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
894                   ISA_MICROMIPS32R6;
895 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
896                   ISA_MICROMIPS32R6;
897 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
898                   ISA_MICROMIPS32R6;
899 def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
900                   ISA_MICROMIPS32R6;
901 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
902 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
903 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
904 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
905 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
906                   ISA_MICROMIPS32R6;
907 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
908                   ISA_MICROMIPS32R6;
909 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
910                   ISA_MICROMIPS32R6;
911 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
912                   ISA_MICROMIPS32R6;
913 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
914                    ISA_MICROMIPS32R6;
915 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
916                    ISA_MICROMIPS32R6;
917 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
918                    ISA_MICROMIPS32R6;
919 def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
920                    ISA_MICROMIPS32R6;
921 def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
922                    ISA_MICROMIPS32R6;
923 def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
924                    ISA_MICROMIPS32R6;
925 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
926                    ISA_MICROMIPS32R6;
927 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
928                    ISA_MICROMIPS32R6;
929 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
930                    ISA_MICROMIPS32R6;
931 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
932                    ISA_MICROMIPS32R6;
933 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
934 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
935 def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
936 def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
937 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
938                      ISA_MICROMIPS32R6;
939 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
940                      ISA_MICROMIPS32R6;
941 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
942                      ISA_MICROMIPS32R6;
943 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
944                      ISA_MICROMIPS32R6;
945 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
946                     ISA_MICROMIPS32R6;
947 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
948                     ISA_MICROMIPS32R6;
949 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
950                     ISA_MICROMIPS32R6;
951 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
952                     ISA_MICROMIPS32R6;
953 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
954                      ISA_MICROMIPS32R6;
955 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
956                      ISA_MICROMIPS32R6;
957 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
958                      ISA_MICROMIPS32R6;
959 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
960                      ISA_MICROMIPS32R6;
961 def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
962                   ISA_MICROMIPS32R6;
963 def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
964                   ISA_MICROMIPS32R6;
965 def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
966                    ISA_MICROMIPS32R6;
967 def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
968                    ISA_MICROMIPS32R6;
969 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
970 def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
971 def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
972 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
973 def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
974 def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6;
975 def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6;
976 def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
977 def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
978 def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
979                   ISA_MICROMIPS32R6;
980 def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
981                   ISA_MICROMIPS32R6;
982 def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
983                   ISA_MICROMIPS32R6;
984 def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
985                   ISA_MICROMIPS32R6;
986 def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
987                   ISA_MICROMIPS32R6;
988 def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
989                   ISA_MICROMIPS32R6;
990 def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
991                   ISA_MICROMIPS32R6;
992 def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
993                    ISA_MICROMIPS32R6;
994 def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
995                 ISA_MICROMIPS32R6;
996 def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
997                   ISA_MICROMIPS32R6;
998 def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
999                    ISA_MICROMIPS32R6;
1000 def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
1001                   ISA_MICROMIPS32R6;
1002 def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
1003                  ISA_MICROMIPS32R6;
1004 }
1005
1006 //===----------------------------------------------------------------------===//
1007 //
1008 // MicroMips instruction aliases
1009 //
1010 //===----------------------------------------------------------------------===//
1011
1012 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1013 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
1014 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1015                                       !strconcat("b", "\t$offset")> {
1016   string DecoderNamespace = "MicroMipsR6";
1017 }
C/C++ LLVM-based compilers that forbids OOTA behaviors