lib/Target/Mips/MicroMips32r6InstrInfo.td

   1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes microMIPSr6 instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 def brtarget26_mm : Operand<OtherVT> {
  15   let EncoderMethod = "getBranchTarget26OpValueMM";
  16   let OperandType = "OPERAND_PCREL";
  17   let DecoderMethod = "DecodeBranchTarget26MM";
  18   let ParserMatchClass = MipsJumpTargetAsmOperand;
  19 }
  20
  21 //===----------------------------------------------------------------------===//
  22 //
  23 // Instruction Encodings
  24 //
  25 //===----------------------------------------------------------------------===//
  26 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
  27 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
  28 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
  29 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
  30 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
  31 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
  32 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
  33 class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
  34 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
  35 class AUI_MMR6_ENC : AUI_FM_MMR6;
  36 class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
  37 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
  38 class BC16_MMR6_ENC : BC16_FM_MM16R6;
  39 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
  40 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
  41 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
  42 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
  43 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
  44 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
  45 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
  46 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
  47 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
  48 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
  49 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
  50 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
  51 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
  52 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
  53 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
  54 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
  55 class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>;
  56 class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">;
  57 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
  58 class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
  59 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
  60 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
  61 class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
  62 class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
  63 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
  64 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
  65 class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>;
  66 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
  67 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
  68 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
  69 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
  70 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
  71 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
  72 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
  73 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
  74 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
  75 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
  76 class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>;
  77 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
  78 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
  79 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
  80 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
  81 class SH16_MMR6_ENC : LOAD_STORE_FM_MM16<0x2a>;
  82 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
  83 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
  84 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
  85 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
  86 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
  87 class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>;
  88 class SWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0xa>;
  89 class SWSP_MMR6_ENC : LOAD_STORE_SP_FM_MM16<0x32>;
  90 class PREFE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b010>;
  91 class CACHEE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b011>;
  92 class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x3c5>;
  93 class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x1ec>;
  94 class LB_MMR6_ENC : LB32_FM_MMR6;
  95 class LBU_MMR6_ENC : LBU32_FM_MMR6;
  96 class LBE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b100>;
  97 class LBUE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b000>;
  98 class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>;
  99 class RDHWR_MMR6_ENC : POOL32A_RDHWR_FM_MMR6;
 100 class WAIT_MMR6_ENC : WAIT_FM_MM, MMR6Arch<"wait">;
 101 class SSNOP_MMR6_ENC : BARRIER_FM_MM<0x1>, MMR6Arch<"ssnop">;
 102 class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6;
 103 class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">;
 104 class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>;
 105 class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">;
 106 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
 107 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
 108 class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
 109 class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
 110 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
 111 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
 112 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
 113 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
 114 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
 115 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
 116 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
 117 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
 118 class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
 119 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
 120 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
 121 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
 122 class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
 123 class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
 124 class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
 125 class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
 126 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
 127 class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
 128 class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
 129 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
 130 class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
 131 class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
 132 class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
 133 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
 134 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
 135 class RECIP_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.s", 0, 0b01001000>;
 136 class RECIP_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.d", 1, 0b01001000>;
 137 class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
 138 class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
 139 class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
 140                                                        0b11001100>;
 141 class ROUND_L_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.d", 1,
 142                                                        0b11001100>;
 143 class ROUND_W_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.s", 0,
 144                                                        0b11101100>;
 145 class ROUND_W_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.d", 1,
 146                                                        0b11101100>;
 147 class SEL_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.s", 0, 0b010111000>;
 148 class SEL_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.d", 1, 0b010111000>;
 149 class SELEQZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.s", 0, 0b000111000>;
 150 class SELEQZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.d", 1, 0b000111000>;
 151 class SELENZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selenz.s", 0, 0b001111000>;
 152 class SELENZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selenz.d", 1, 0b001111000>;
 153 class CLASS_S_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.s", 0, 0b001100000>;
 154 class CLASS_D_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.d", 1, 0b001100000>;
 155
 156 class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
 157 class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
 158 class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16;
 159 class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
 160 class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
 161 class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
 162 class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
 163 class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
 164 class LI16_MMR6_ENC : LI_FM_MM16;
 165 class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
 166 class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
 167 class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
 168 class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
 169
 170 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
 171                                   RegisterOperand GPROpnd>
 172     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 173   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 174   dag OutOperandList = (outs);
 175   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
 176   list<Register> Defs = [AT];
 177 }
 178
 179 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
 180                                                       GPR32Opnd> {
 181   list<Register> Defs = [RA];
 182 }
 183
 184 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
 185                                                       GPR32Opnd> {
 186   list<Register> Defs = [RA];
 187 }
 188
 189 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
 190                                                       GPR32Opnd> {
 191   list<Register> Defs = [RA];
 192 }
 193
 194 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
 195                                                       GPR32Opnd> {
 196   list<Register> Defs = [RA];
 197 }
 198
 199 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
 200                                                       GPR32Opnd> {
 201   list<Register> Defs = [RA];
 202 }
 203
 204 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
 205                                                       GPR32Opnd> {
 206   list<Register> Defs = [RA];
 207 }
 208
 209 /// Floating Point Instructions
 210 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
 211 class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
 212 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
 213 class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
 214 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
 215 class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
 216 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
 217 class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
 218 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
 219 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
 220 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
 221 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
 222 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
 223 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
 224 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
 225 class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
 226 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
 227 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
 228 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
 229 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
 230 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
 231 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
 232 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
 233 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
 234
 235 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
 236 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
 237 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
 238 class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
 239 class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
 240 class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
 241 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
 242 class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
 243 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
 244 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
 245
 246 //===----------------------------------------------------------------------===//
 247 //
 248 // Instruction Descriptions
 249 //
 250 //===----------------------------------------------------------------------===//
 251
 252 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
 253 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
 254 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
 255 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
 256 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
 257 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
 258 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
 259
 260 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
 261     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 262   dag InOperandList = (ins opnd:$offset);
 263   dag OutOperandList = (outs);
 264   string AsmString = !strconcat(instr_asm, "\t$offset");
 265   bit isBarrier = 1;
 266 }
 267
 268 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm> {
 269   bit isCall = 1;
 270   list<Register> Defs = [RA];
 271 }
 272 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm>;
 273
 274 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
 275                                        !strconcat("bc16", "\t$offset"), [],
 276                                        II_BC, FrmI>,
 277                        MMR6Arch<"bc16">, MicroMipsR6Inst16 {
 278   let isBranch = 1;
 279   let isTerminator = 1;
 280   let isBarrier = 1;
 281   let hasDelaySlot = 0;
 282   let AdditionalPredicates = [RelocPIC];
 283   let Defs = [AT];
 284 }
 285
 286 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
 287     : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>, MMR6Arch<instr_asm> {
 288   let isBranch = 1;
 289   let isTerminator = 1;
 290   let hasDelaySlot = 0;
 291   let Defs = [AT];
 292 }
 293 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
 294 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
 295
 296 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
 297 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
 298
 299 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 300     : MMR6Arch<instr_asm> {
 301   dag OutOperandList = (outs GPROpnd:$rd);
 302   dag InOperandList = (ins GPROpnd:$rt);
 303   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 304   list<dag> Pattern = [];
 305 }
 306
 307 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
 308
 309 class BRK_MMR6_DESC : BRK_FT<"break">;
 310
 311 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
 312                            RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
 313   dag OutOperandList = (outs);
 314   dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
 315   string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
 316   list<dag> Pattern = [];
 317   string DecoderMethod = "DecodeCacheOpMM";
 318 }
 319
 320 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
 321 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
 322
 323 class PREFE_CACHEE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
 324                                   RegisterOperand GPROpnd> :
 325                                   CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd,
 326                                   GPROpnd> {
 327   string DecoderMethod = "DecodePrefeOpMM";
 328 }
 329
 330 class PREFE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"prefe", mem_mm_9, GPR32Opnd>;
 331 class CACHEE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"cachee", mem_mm_9, GPR32Opnd>;
 332
 333 class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
 334                             RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
 335   dag OutOperandList = (outs GPROpnd:$rt);
 336   dag InOperandList = (ins MemOpnd:$addr);
 337   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 338   string DecoderMethod = "DecodeLoadByte15";
 339   bit mayLoad = 1;
 340 }
 341 class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd>;
 342 class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd>;
 343
 344 class LBE_LBUE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
 345                               RegisterOperand GPROpnd>
 346     : LB_LBU_MMR6_DESC_BASE<instr_asm, MemOpnd, GPROpnd> {
 347   let DecoderMethod = "DecodeLoadByte9";
 348 }
 349 class LBE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbe", mem_mm_9, GPR32Opnd>;
 350 class LBUE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbue", mem_mm_9, GPR32Opnd>;
 351
 352 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 353     : MMR6Arch<instr_asm> {
 354   dag OutOperandList = (outs GPROpnd:$rt);
 355   dag InOperandList = (ins GPROpnd:$rs);
 356   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 357 }
 358
 359 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
 360 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
 361
 362 class EHB_MMR6_DESC : Barrier<"ehb">;
 363 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
 364
 365 class ERET_MMR6_DESC : ER_FT<"eret">;
 366 class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
 367
 368 class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
 369     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
 370                       [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
 371       MMR6Arch<opstr>, MicroMipsR6Inst16 {
 372   let isCall = 1;
 373   let hasDelaySlot = 0;
 374   let Defs = [RA];
 375 }
 376 class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
 377
 378 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
 379                                      RegisterOperand GPROpnd>
 380     : MMR6Arch<opstr> {
 381   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 382   string AsmString = !strconcat(opstr, "\t$rt, $offset");
 383   list<dag> Pattern = [];
 384   bit isTerminator = 1;
 385   bit hasDelaySlot = 0;
 386 }
 387
 388 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
 389                                                        GPR32Opnd> {
 390   bit isCall = 1;
 391   list<Register> Defs = [RA];
 392 }
 393
 394 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
 395                                                      GPR32Opnd> {
 396   bit isBarrier = 1;
 397   list<Register> Defs = [AT];
 398 }
 399
 400 class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
 401     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
 402                       [], II_JR, FrmR>,
 403       MMR6Arch<opstr>, MicroMipsR6Inst16 {
 404   let hasDelaySlot = 0;
 405   let isBranch = 1;
 406   let isIndirectBranch = 1;
 407 }
 408 class JRC16_MMR6_DESC : JRC16_MMR6_DESC_BASE<"jrc16", GPR32Opnd>;
 409
 410 class JRCADDIUSP_MMR6_DESC
 411     : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm",
 412                       [], II_JRADDIUSP, FrmR>,
 413       MMR6Arch<"jrcaddiusp">, MicroMipsR6Inst16 {
 414   let hasDelaySlot = 0;
 415   let isTerminator = 1;
 416   let isBarrier = 1;
 417   let isBranch = 1;
 418   let isIndirectBranch = 1;
 419 }
 420
 421 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 422                       Operand ImmOpnd>  : MMR6Arch<instr_asm> {
 423   dag OutOperandList = (outs GPROpnd:$rd);
 424   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
 425   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
 426   list<dag> Pattern = [];
 427 }
 428
 429 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
 430
 431 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 432     : MMR6Arch<instr_asm> {
 433   dag OutOperandList = (outs GPROpnd:$rt);
 434   dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
 435   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
 436   list<dag> Pattern = [];
 437 }
 438
 439 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
 440
 441 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
 442 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
 443 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 444     : MMR6Arch<instr_asm> {
 445   dag OutOperandList = (outs GPROpnd:$rt);
 446   dag InOperandList = (ins simm16:$imm);
 447   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 448   list<dag> Pattern = [];
 449 }
 450
 451 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
 452 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
 453
 454 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 455                          Operand ImmOpnd> : MMR6Arch<instr_asm> {
 456   dag OutOperandList = (outs GPROpnd:$rd);
 457   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
 458   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
 459   list<dag> Pattern = [];
 460 }
 461
 462 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1>;
 463
 464 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 465                            Operand ImmOpnd> : MMR6Arch<instr_asm> {
 466   dag OutOperandList = (outs GPROpnd:$rt);
 467   dag InOperandList = (ins ImmOpnd:$imm);
 468   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 469   list<dag> Pattern = [];
 470 }
 471
 472 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
 473 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
 474
 475 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 476     : MMR6Arch<instr_asm> {
 477   dag OutOperandList = (outs GPROpnd:$rd);
 478   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
 479   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 480   list<dag> Pattern = [];
 481 }
 482
 483 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
 484 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
 485 class PAUSE_MMR6_DESC : Barrier<"pause">;
 486 class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
 487   dag OutOperandList = (outs GPR32Opnd:$rt);
 488   dag InOperandList = (ins HWRegsOpnd:$rs, uimm3:$sel);
 489   string AsmString = !strconcat("rdhwr", "\t$rt, $rs, $sel");
 490   list<dag> Pattern = [];
 491   InstrItinClass Itinerary = II_RDHWR;
 492   Format Form = FrmR;
 493 }
 494
 495 class WAIT_MMR6_DESC : WaitMM<"wait">;
 496 class SSNOP_MMR6_DESC : Barrier<"ssnop">;
 497 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
 498 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
 499 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
 500 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
 501 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
 502 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
 503 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
 504 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
 505 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
 506 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
 507 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
 508 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
 509
 510 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
 511                   SDPatternOperator OpNode = null_frag,
 512                   InstrItinClass Itin = NoItinerary,
 513                   ComplexPattern Addr = addr> :
 514   InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
 515          [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
 516   let DecoderMethod = "DecodeMem";
 517   let mayStore = 1;
 518 }
 519 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
 520 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9>;
 521
 522 class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
 523     : MMR6Arch<instr_asm> {
 524   dag InOperandList = (ins RO:$rs);
 525   dag OutOperandList = (outs RO:$rt);
 526   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 527   list<dag> Pattern = [];
 528   Format f = FrmR;
 529   string BaseOpcode = instr_asm;
 530   bit hasSideEffects = 0;
 531 }
 532 class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd>;
 533 class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd>;
 534
 535 /// Floating Point Instructions
 536 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
 537                             InstrItinClass Itin, bit isComm,
 538                             SDPatternOperator OpNode = null_frag> : HARDFLOAT {
 539   dag OutOperandList = (outs RC:$fd);
 540   dag InOperandList = (ins RC:$ft, RC:$fs);
 541   string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
 542   list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
 543   InstrItinClass Itinerary = Itin;
 544   bit isCommutable = isComm;
 545 }
 546 class FADD_S_MMR6_DESC
 547   : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
 548 class FADD_D_MMR6_DESC
 549   : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
 550 class FSUB_S_MMR6_DESC
 551   : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
 552 class FSUB_D_MMR6_DESC
 553   : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
 554 class FMUL_S_MMR6_DESC
 555   : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
 556 class FMUL_D_MMR6_DESC
 557   : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
 558 class FDIV_S_MMR6_DESC
 559   : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
 560 class FDIV_D_MMR6_DESC
 561   : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
 562 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
 563 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
 564 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
 565 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
 566
 567 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 568                                RegisterOperand SrcRC, InstrItinClass Itin,
 569                                SDPatternOperator OpNode = null_frag>
 570                                : HARDFLOAT, NeverHasSideEffects {
 571   dag OutOperandList = (outs DstRC:$ft);
 572   dag InOperandList = (ins SrcRC:$fs);
 573   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 574   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 575   InstrItinClass Itinerary = Itin;
 576   Format Form = FrmFR;
 577 }
 578 class FMOV_S_MMR6_DESC
 579   : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
 580 class FMOV_D_MMR6_DESC
 581   : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
 582 class FNEG_S_MMR6_DESC
 583   : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
 584 class FNEG_D_MMR6_DESC
 585   : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
 586
 587 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT;
 588 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT;
 589 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT;
 590 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT;
 591
 592 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT;
 593 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT;
 594 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT;
 595 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT;
 596
 597 class CVT_MMR6_DESC_BASE<
 598     string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
 599     InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
 600     : HARDFLOAT, NeverHasSideEffects {
 601   dag OutOperandList = (outs DstRC:$ft);
 602   dag InOperandList = (ins SrcRC:$fs);
 603   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 604   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 605   InstrItinClass Itinerary = Itin;
 606   Format Form = FrmFR;
 607 }
 608
 609 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
 610                                              II_CVT>;
 611 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
 612                                              II_CVT>;
 613 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
 614                                              II_CVT>;
 615 class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
 616                                              II_CVT>;
 617 class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
 618                                              II_CVT>;
 619 class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
 620                                              II_CVT>;
 621 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
 622                                              II_CVT>, FGR_64;
 623 class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
 624                                              II_CVT>;
 625 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
 626                                              II_CVT>;
 627 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
 628                                              II_CVT>, FGR_64;
 629
 630 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
 631                        RegisterOperand FGROpnd> {
 632   def CMP_AF_#NAME : POOL32F_CMP_FM<
 633       !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
 634       CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 635       ISA_MICROMIPS32R6;
 636   def CMP_UN_#NAME : POOL32F_CMP_FM<
 637       !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
 638       CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 639       ISA_MICROMIPS32R6;
 640   def CMP_EQ_#NAME : POOL32F_CMP_FM<
 641       !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
 642       CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 643       ISA_MICROMIPS32R6;
 644   def CMP_UEQ_#NAME : POOL32F_CMP_FM<
 645       !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
 646       CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 647       ISA_MICROMIPS32R6;
 648   def CMP_LT_#NAME : POOL32F_CMP_FM<
 649       !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
 650       CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 651       ISA_MICROMIPS32R6;
 652   def CMP_ULT_#NAME : POOL32F_CMP_FM<
 653       !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
 654       CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 655       ISA_MICROMIPS32R6;
 656   def CMP_LE_#NAME : POOL32F_CMP_FM<
 657       !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
 658       CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 659       ISA_MICROMIPS32R6;
 660   def CMP_ULE_#NAME : POOL32F_CMP_FM<
 661       !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
 662       CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 663       ISA_MICROMIPS32R6;
 664   def CMP_SAF_#NAME : POOL32F_CMP_FM<
 665       !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
 666       CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 667       ISA_MICROMIPS32R6;
 668   def CMP_SUN_#NAME : POOL32F_CMP_FM<
 669       !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
 670       CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 671       ISA_MICROMIPS32R6;
 672   def CMP_SEQ_#NAME : POOL32F_CMP_FM<
 673       !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
 674       CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 675       ISA_MICROMIPS32R6;
 676   def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
 677       !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
 678       CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 679       ISA_MICROMIPS32R6;
 680   def CMP_SLT_#NAME : POOL32F_CMP_FM<
 681       !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
 682       CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 683       ISA_MICROMIPS32R6;
 684   def CMP_SULT_#NAME : POOL32F_CMP_FM<
 685       !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
 686       CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 687       ISA_MICROMIPS32R6;
 688   def CMP_SLE_#NAME : POOL32F_CMP_FM<
 689       !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
 690       CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 691       ISA_MICROMIPS32R6;
 692   def CMP_SULE_#NAME : POOL32F_CMP_FM<
 693       !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
 694       CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
 695       ISA_MICROMIPS32R6;
 696 }
 697
 698 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 699                              RegisterOperand SrcRC, InstrItinClass Itin,
 700                              SDPatternOperator OpNode = null_frag>
 701     : HARDFLOAT, NeverHasSideEffects {
 702   dag OutOperandList = (outs DstRC:$ft);
 703   dag InOperandList  = (ins SrcRC:$fs);
 704   string AsmString   = !strconcat(instr_asm, "\t$ft, $fs");
 705   list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 706   InstrItinClass Itinerary = Itin;
 707   Format Form = FrmFR;
 708   list<Predicate> EncodingPredicates = [HasStdEnc];
 709 }
 710
 711 class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd,
 712                                                 II_ABS, fabs>;
 713 class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd,
 714                                                 II_ABS, fabs>;
 715 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
 716                                                     FGR32Opnd, II_FLOOR>;
 717 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
 718                                                     FGR64Opnd, II_FLOOR>;
 719 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
 720                                                     FGR32Opnd, II_FLOOR>;
 721 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
 722                                                     AFGR64Opnd, II_FLOOR>;
 723 class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
 724                                                    FGR32Opnd, II_CEIL>;
 725 class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
 726                                                    FGR64Opnd, II_CEIL>;
 727 class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
 728                                                    FGR32Opnd, II_CEIL>;
 729 class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
 730                                                    AFGR64Opnd, II_CEIL>;
 731 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
 732                                                     FGR32Opnd, II_TRUNC>;
 733 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
 734                                                     FGR64Opnd, II_TRUNC>;
 735 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
 736                                                     FGR32Opnd, II_TRUNC>;
 737 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
 738                                                     AFGR64Opnd, II_TRUNC>;
 739 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
 740                                                  II_SQRT_S, fsqrt>;
 741 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
 742                                                  II_SQRT_D, fsqrt>;
 743 class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
 744                                                   FGR32Opnd, II_TRUNC>;
 745 class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
 746                                                   AFGR64Opnd, II_TRUNC>;
 747 class RECIP_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.s", FGR32Opnd,
 748                                                  FGR32Opnd, II_ROUND>;
 749 class RECIP_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.d", FGR32Opnd, FGR32Opnd,
 750                                                  II_ROUND>;
 751 class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
 752                                                    FGR32Opnd, II_ROUND>;
 753 class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
 754                                                    FGR64Opnd, II_ROUND>;
 755 class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
 756                                                    FGR32Opnd, II_ROUND>;
 757 class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
 758                                                    FGR64Opnd, II_ROUND>;
 759
 760 class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
 761 class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {
 762   // We must insert a SUBREG_TO_REG around $fd_in
 763   bit usesCustomInserter = 1;
 764 }
 765
 766 class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
 767 class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
 768 class SELENZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
 769 class SELENZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
 770 class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
 771 class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
 772 class CLASS_S_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
 773 class CLASS_D_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
 774
 775 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO>
 776     : Store<opstr, RO>, MMR6Arch<opstr> {
 777   let DecoderMethod = "DecodeMemMMImm16";
 778 }
 779 class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>;
 780
 781 class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
 782     : MMR6Arch<instr_asm>, MipsR6Inst {
 783   dag OutOperandList = (outs);
 784   dag InOperandList = (ins RO:$rt, mem_mm_9:$addr);
 785   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 786   string DecoderMethod = "DecodeStoreEvaOpMM";
 787   bit mayStore = 1;
 788 }
 789 class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd>;
 790 class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>;
 791 class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>;
 792 class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>;
 793 class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
 794             MMR6Arch<instr_asm>, MipsR6Inst {
 795   dag OutOperandList = (outs RO:$rt);
 796   dag InOperandList = (ins mem_mm_12:$addr);
 797   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 798   string DecoderMethod = "DecodeMemMMImm9";
 799   bit mayLoad = 1;
 800 }
 801 class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
 802 class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
 803 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
 804       MMR6Arch<"addu16">;
 805 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
 806       MMR6Arch<"and16">;
 807 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
 808       MMR6Arch<"andi16">;
 809 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">;
 810 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
 811       MMR6Arch<"or16">;
 812 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
 813       MMR6Arch<"sll16">;
 814 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
 815       MMR6Arch<"srl16">;
 816 class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"srl16">,
 817       MicroMipsR6Inst16;
 818 class LI16_MMR6_DESC : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>,
 819       MMR6Arch<"srl16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
 820 class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"srl16">,
 821       MicroMipsR6Inst16;
 822 class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">,
 823       MicroMipsR6Inst16;
 824 class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
 825       MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
 826 class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
 827       MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
 828
 829 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
 830   dag OutOperandList = (outs GPR32Opnd:$rt);
 831   dag InOperandList = (ins mem:$addr);
 832   string AsmString = "lw\t$rt, $addr";
 833   let DecoderMethod = "DecodeMemMMImm16";
 834   let canFoldAsLoad = 1;
 835   let mayLoad = 1;
 836   list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
 837   InstrItinClass Itinerary = II_LW;
 838 }
 839
 840 class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
 841   dag OutOperandList = (outs GPR32Opnd:$rt);
 842   dag InOperandList = (ins uimm16:$imm16);
 843   string AsmString = "lui\t$rt, $imm16";
 844   list<dag> Pattern = [];
 845   bit hasSideEffects = 0;
 846   bit isReMaterializable = 1;
 847   InstrItinClass Itinerary = II_LUI;
 848   Format Form = FrmI;
 849 }
 850
 851 class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
 852   dag OutOperandList = (outs);
 853   dag InOperandList = (ins i32imm:$stype);
 854   string AsmString = !strconcat("sync", "\t$stype");
 855   list<dag> Pattern = [(MipsSync imm:$stype)];
 856   InstrItinClass Itinerary = NoItinerary;
 857   bit HasSideEffects = 1;
 858 }
 859
 860 class SYNCI_MMR6_DESC : SYNCI_FT<"synci"> {
 861   let DecoderMethod = "DecodeSynciR6";
 862 }
 863
 864 class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst {
 865   dag OutOperandList = (outs GPR32Opnd:$rt);
 866   dag InOperandList = (ins GPR32Opnd:$rd);
 867   string AsmString = !strconcat("rdpgpr", "\t$rt, $rd");
 868 }
 869
 870 class SDBBP_MMR6_DESC : MipsR6Inst {
 871   dag OutOperandList = (outs);
 872   dag InOperandList = (ins uimm20:$code_);
 873   string AsmString = !strconcat("sdbbp", "\t$code_");
 874   list<dag> Pattern = [];
 875 }
 876
 877 class LWM16_MMR6_DESC
 878     : MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
 879                       !strconcat("lwm16", "\t$rt, $addr"), [],
 880                       NoItinerary, FrmI>,
 881       MMR6Arch<"lwm16">, MicroMipsR6Inst16 {
 882   let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
 883   let mayLoad = 1;
 884   InstrItinClass Itin = NoItinerary;
 885   ComplexPattern Addr = addr;
 886 }
 887
 888 class SWM16_MMR6_DESC
 889     : MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
 890                       !strconcat("swm16", "\t$rt, $addr"), [],
 891                       NoItinerary, FrmI>,
 892       MMR6Arch<"swm16">, MicroMipsR6Inst16 {
 893   let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
 894   let mayStore = 1;
 895   InstrItinClass Itin = NoItinerary;
 896   ComplexPattern Addr = addr;
 897 }
 898
 899 class SB16_MMR6_DESC_BASE<string opstr, DAGOperand RTOpnd, DAGOperand RO,
 900                           SDPatternOperator OpNode, InstrItinClass Itin,
 901                           Operand MemOpnd>
 902     : MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
 903                       !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI>,
 904       MMR6Arch<opstr>, MicroMipsR6Inst16 {
 905   let DecoderMethod = "DecodeMemMMImm4";
 906   let mayStore = 1;
 907 }
 908 class SB16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, GPRMM16Opnd,
 909                                            truncstorei8, II_SB, mem_mm_4>;
 910 class SH16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, GPRMM16Opnd,
 911                                            truncstorei16, II_SH, mem_mm_4_lsl1>;
 912 class SW16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, GPRMM16Opnd,
 913                                            store, II_SW, mem_mm_4_lsl2>;
 914
 915 class SWSP_MMR6_DESC
 916     : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
 917                       !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
 918       MMR6Arch<"sw">, MicroMipsR6Inst16 {
 919   let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
 920   let mayStore = 1;
 921 }
 922
 923 //===----------------------------------------------------------------------===//
 924 //
 925 // Instruction Definitions
 926 //
 927 //===----------------------------------------------------------------------===//
 928
 929 let DecoderNamespace = "MicroMipsR6" in {
 930 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
 931 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
 932 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
 933 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
 934                    ISA_MICROMIPS32R6;
 935 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
 936                   ISA_MICROMIPS32R6;
 937 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
 938 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
 939 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
 940 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
 941 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
 942 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
 943 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
 944 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
 945 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
 946                    ISA_MICROMIPS32R6;
 947 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
 948                    ISA_MICROMIPS32R6;
 949 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
 950                    ISA_MICROMIPS32R6;
 951 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
 952                    ISA_MICROMIPS32R6;
 953 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
 954                    ISA_MICROMIPS32R6;
 955 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
 956                    ISA_MICROMIPS32R6;
 957 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
 958                    ISA_MICROMIPS32R6;
 959 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
 960                    ISA_MICROMIPS32R6;
 961 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
 962                    ISA_MICROMIPS32R6;
 963 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
 964 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
 965 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
 966 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
 967 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
 968 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
 969 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
 970 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
 971 def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
 972 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
 973                   ISA_MICROMIPS32R6;
 974 def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
 975                    ISA_MICROMIPS32R6;
 976 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
 977 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
 978 def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
 979 def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
 980                       ISA_MICROMIPS32R6;
 981 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
 982 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
 983 def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6;
 984 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
 985 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
 986 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
 987 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
 988 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
 989 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
 990 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
 991 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
 992 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
 993 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
 994 def SB16_MMR6 : StdMMR6Rel, SB16_MMR6_DESC, SB16_MMR6_ENC, ISA_MICROMIPS32R6;
 995 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
 996 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
 997 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
 998                   ISA_MICROMIPS32R6;
 999 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
1000                   ISA_MICROMIPS32R6;
1001 def SH16_MMR6 : StdMMR6Rel, SH16_MMR6_DESC, SH16_MMR6_ENC, ISA_MICROMIPS32R6;
1002 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
1003 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
1004 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
1005 def SW16_MMR6 : StdMMR6Rel, SW16_MMR6_DESC, SW16_MMR6_ENC, ISA_MICROMIPS32R6;
1006 def SWM16_MMR6 : StdMMR6Rel, SWM16_MMR6_DESC, SWM16_MMR6_ENC, ISA_MICROMIPS32R6;
1007 def SWSP_MMR6 : StdMMR6Rel, SWSP_MMR6_DESC, SWSP_MMR6_ENC, ISA_MICROMIPS32R6;
1008 def PREFE_MMR6 : StdMMR6Rel, PREFE_MMR6_ENC, PREFE_MMR6_DESC, ISA_MICROMIPS32R6;
1009 def CACHEE_MMR6 : StdMMR6Rel, CACHEE_MMR6_ENC, CACHEE_MMR6_DESC,
1010                   ISA_MICROMIPS32R6;
1011 def WRPGPR_MMR6 : StdMMR6Rel, WRPGPR_MMR6_ENC, WRPGPR_MMR6_DESC,
1012                   ISA_MICROMIPS32R6;
1013 def WSBH_MMR6 : StdMMR6Rel, WSBH_MMR6_ENC, WSBH_MMR6_DESC, ISA_MICROMIPS32R6;
1014 def LB_MMR6 : R6MMR6Rel, LB_MMR6_ENC, LB_MMR6_DESC, ISA_MICROMIPS32R6;
1015 def LBU_MMR6 : R6MMR6Rel, LBU_MMR6_ENC, LBU_MMR6_DESC, ISA_MICROMIPS32R6;
1016 def LBE_MMR6 : R6MMR6Rel, LBE_MMR6_ENC, LBE_MMR6_DESC, ISA_MICROMIPS32R6;
1017 def LBUE_MMR6 : R6MMR6Rel, LBUE_MMR6_ENC, LBUE_MMR6_DESC, ISA_MICROMIPS32R6;
1018 def PAUSE_MMR6 : StdMMR6Rel, PAUSE_MMR6_DESC, PAUSE_MMR6_ENC, ISA_MICROMIPS32R6;
1019 def RDHWR_MMR6 : R6MMR6Rel, RDHWR_MMR6_DESC, RDHWR_MMR6_ENC, ISA_MICROMIPS32R6;
1020 def WAIT_MMR6 : StdMMR6Rel, WAIT_MMR6_DESC, WAIT_MMR6_ENC, ISA_MICROMIPS32R6;
1021 def SSNOP_MMR6 : StdMMR6Rel, SSNOP_MMR6_DESC, SSNOP_MMR6_ENC, ISA_MICROMIPS32R6;
1022 def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6;
1023 def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
1024 def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
1025                   ISA_MICROMIPS32R6;
1026 def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
1027 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
1028 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
1029 let DecoderMethod = "DecodeMemMMImm16" in {
1030   def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
1031 }
1032 let DecoderMethod = "DecodeMemMMImm9" in {
1033   def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
1034 }
1035 /// Floating Point Instructions
1036 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
1037                   ISA_MICROMIPS32R6;
1038 def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
1039                   ISA_MICROMIPS32R6;
1040 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
1041                   ISA_MICROMIPS32R6;
1042 def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
1043                   ISA_MICROMIPS32R6;
1044 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
1045                   ISA_MICROMIPS32R6;
1046 def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
1047                   ISA_MICROMIPS32R6;
1048 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
1049                   ISA_MICROMIPS32R6;
1050 def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
1051                   ISA_MICROMIPS32R6;
1052 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
1053                    ISA_MICROMIPS32R6;
1054 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
1055                    ISA_MICROMIPS32R6;
1056 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
1057                    ISA_MICROMIPS32R6;
1058 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
1059                    ISA_MICROMIPS32R6;
1060 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
1061                   ISA_MICROMIPS32R6;
1062 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
1063                   ISA_MICROMIPS32R6;
1064 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
1065                   ISA_MICROMIPS32R6;
1066 def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
1067                   ISA_MICROMIPS32R6;
1068 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
1069 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
1070 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
1071 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
1072 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
1073                   ISA_MICROMIPS32R6;
1074 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
1075                   ISA_MICROMIPS32R6;
1076 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
1077                   ISA_MICROMIPS32R6;
1078 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
1079                   ISA_MICROMIPS32R6;
1080 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
1081                    ISA_MICROMIPS32R6;
1082 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
1083                    ISA_MICROMIPS32R6;
1084 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
1085                    ISA_MICROMIPS32R6;
1086 def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
1087                    ISA_MICROMIPS32R6;
1088 def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
1089                    ISA_MICROMIPS32R6;
1090 def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
1091                    ISA_MICROMIPS32R6;
1092 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
1093                    ISA_MICROMIPS32R6;
1094 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
1095                    ISA_MICROMIPS32R6;
1096 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
1097                    ISA_MICROMIPS32R6;
1098 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
1099                    ISA_MICROMIPS32R6;
1100 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
1101 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
1102 def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
1103 def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
1104 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
1105                      ISA_MICROMIPS32R6;
1106 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
1107                      ISA_MICROMIPS32R6;
1108 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
1109                      ISA_MICROMIPS32R6;
1110 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
1111                      ISA_MICROMIPS32R6;
1112 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
1113                     ISA_MICROMIPS32R6;
1114 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
1115                     ISA_MICROMIPS32R6;
1116 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
1117                     ISA_MICROMIPS32R6;
1118 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
1119                     ISA_MICROMIPS32R6;
1120 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
1121                      ISA_MICROMIPS32R6;
1122 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
1123                      ISA_MICROMIPS32R6;
1124 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
1125                      ISA_MICROMIPS32R6;
1126 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
1127                      ISA_MICROMIPS32R6;
1128 def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
1129                   ISA_MICROMIPS32R6;
1130 def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
1131                   ISA_MICROMIPS32R6;
1132 def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
1133                    ISA_MICROMIPS32R6;
1134 def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
1135                    ISA_MICROMIPS32R6;
1136 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
1137 def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
1138 def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
1139 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
1140 def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
1141 def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6;
1142 def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6;
1143 def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
1144 def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
1145 def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
1146                   ISA_MICROMIPS32R6;
1147 def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
1148                   ISA_MICROMIPS32R6;
1149 def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
1150                   ISA_MICROMIPS32R6;
1151 def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
1152                   ISA_MICROMIPS32R6;
1153 def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
1154                   ISA_MICROMIPS32R6;
1155 def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
1156                   ISA_MICROMIPS32R6;
1157 def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
1158                   ISA_MICROMIPS32R6;
1159 def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
1160                    ISA_MICROMIPS32R6;
1161 def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
1162                 ISA_MICROMIPS32R6;
1163 def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
1164                   ISA_MICROMIPS32R6;
1165 def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
1166                    ISA_MICROMIPS32R6;
1167 def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
1168                   ISA_MICROMIPS32R6;
1169 def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
1170                  ISA_MICROMIPS32R6;
1171 def RECIP_S_MMR6 : StdMMR6Rel, RECIP_S_MMR6_ENC, RECIP_S_MMR6_DESC,
1172                    ISA_MICROMIPS32R6;
1173 def RECIP_D_MMR6 : StdMMR6Rel, RECIP_D_MMR6_ENC, RECIP_D_MMR6_DESC, ISA_MICROMIPS32R6;
1174 def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
1175                   ISA_MICROMIPS32R6;
1176 def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6;
1177 def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC,
1178                      ISA_MICROMIPS32R6;
1179 def ROUND_L_D_MMR6 : StdMMR6Rel, ROUND_L_D_MMR6_ENC, ROUND_L_D_MMR6_DESC,
1180                      ISA_MICROMIPS32R6;
1181 def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W_S_MMR6_ENC, ROUND_W_S_MMR6_DESC,
1182                      ISA_MICROMIPS32R6;
1183 def ROUND_W_D_MMR6 : StdMMR6Rel, ROUND_W_D_MMR6_ENC, ROUND_W_D_MMR6_DESC,
1184                      ISA_MICROMIPS32R6;
1185 def SEL_S_MMR6 : StdMMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6;
1186 def SEL_D_MMR6 : StdMMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6;
1187 def SELEQZ_S_MMR6 : StdMMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC,
1188                     ISA_MICROMIPS32R6;
1189 def SELEQZ_D_MMR6 : StdMMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC,
1190                     ISA_MICROMIPS32R6;
1191 def SELENZ_S_MMR6 : StdMMR6Rel, SELENZ_S_MMR6_ENC, SELENZ_S_MMR6_DESC,
1192                     ISA_MICROMIPS32R6;
1193 def SELENZ_D_MMR6 : StdMMR6Rel, SELENZ_D_MMR6_ENC, SELENZ_D_MMR6_DESC,
1194                     ISA_MICROMIPS32R6;
1195 def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC,
1196                    ISA_MICROMIPS32R6;
1197 def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC,
1198                    ISA_MICROMIPS32R6;
1199 }
1200
1201 //===----------------------------------------------------------------------===//
1202 //
1203 // MicroMips instruction aliases
1204 //
1205 //===----------------------------------------------------------------------===//
1206
1207 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1208 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
1209 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1210                                       !strconcat("b", "\t$offset")> {
1211   string DecoderNamespace = "MicroMipsR6";
1212 }
1213 def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6;
1214 def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6;
1215 def : MipsInstAlias<"rdhwr $rt, $rs",
1216                     (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
1217                     ISA_MICROMIPS32R6;
1218
1219 //===----------------------------------------------------------------------===//
1220 //
1221 // MicroMips arbitrary patterns that map to one or more instructions
1222 //
1223 //===----------------------------------------------------------------------===//
1224
1225 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
1226               (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;