1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes microMIPSr6 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 // Instruction Encodings
18 //===----------------------------------------------------------------------===//
19 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
20 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
21 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
22 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
23 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
24 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
25 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
26 class AUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11110>;
27 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
28 class AUI_MMR6_ENC : AUI_FM_MMR6;
29 class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>;
30 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
31 class BC16_MMR6_ENC : BC16_FM_MM16R6;
32 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
33 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
34 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
35 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
36 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
37 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
38 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
39 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
40 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
41 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
42 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
43 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
44 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
45 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
46 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
47 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
48 class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>;
49 class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">;
50 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
51 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
52 class JIC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101000>;
53 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
54 class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>;
55 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
56 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
57 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
58 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
59 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
60 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
61 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
62 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
63 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
64 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
65 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
66 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
67 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
68 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
69 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
70 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
71 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
72 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
73 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
74 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
75 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
76 class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
77 class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
78 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
79 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
80 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
81 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
82 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
83 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
84 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
85 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
86 class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
87 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
88 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
89 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
90 class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
91 class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
92 class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
93 class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
95 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
96 RegisterOperand GPROpnd>
97 : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
98 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
99 dag OutOperandList = (outs);
100 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
101 list<Register> Defs = [AT];
104 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
106 list<Register> Defs = [RA];
109 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
111 list<Register> Defs = [RA];
114 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
116 list<Register> Defs = [RA];
119 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
121 list<Register> Defs = [RA];
124 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
126 list<Register> Defs = [RA];
129 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
131 list<Register> Defs = [RA];
134 /// Floating Point Instructions
135 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
136 class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
137 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
138 class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
139 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
140 class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
141 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
142 class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
143 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
144 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
145 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
146 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
147 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
148 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
149 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
150 class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
151 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
152 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
153 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
154 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
155 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
156 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
157 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
158 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
160 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
161 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
162 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
163 class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
164 class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
165 class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
166 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
167 class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
168 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
169 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
171 //===----------------------------------------------------------------------===//
173 // Operand Definitions
175 //===----------------------------------------------------------------------===//
177 def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
178 let Name = "MemOffsetSimm9GPR";
179 let SuperClasses = [MipsMemAsmOperand];
180 let RenderMethod = "addMemOperands";
181 let ParserMethod = "parseMemOperand";
182 let PredicateMethod = "isMemWithSimmOffsetGPR<9>";
185 def mem_simm9gpr : mem_generic {
186 let MIOperandInfo = (ops ptr_rc, simm9);
187 let EncoderMethod = "getMemEncoding";
188 let ParserMatchClass = MipsMemSimm9GPRAsmOperand;
191 //===----------------------------------------------------------------------===//
193 // Instruction Descriptions
195 //===----------------------------------------------------------------------===//
197 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
198 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
199 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
200 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
201 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
202 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
203 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
205 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
206 : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
207 dag InOperandList = (ins opnd:$offset);
208 dag OutOperandList = (outs);
209 string AsmString = !strconcat(instr_asm, "\t$offset");
213 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
215 list<Register> Defs = [RA];
217 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
219 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
220 !strconcat("bc16", "\t$offset"), [],
222 MMR6Arch<"bc16">, MicroMipsR6Inst16 {
224 let isTerminator = 1;
226 let hasDelaySlot = 0;
227 let AdditionalPredicates = [RelocPIC];
231 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
232 : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>, MMR6Arch<instr_asm> {
234 let isTerminator = 1;
235 let hasDelaySlot = 0;
238 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
239 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
241 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
242 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
244 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
245 : MMR6Arch<instr_asm> {
246 dag OutOperandList = (outs GPROpnd:$rd);
247 dag InOperandList = (ins GPROpnd:$rt);
248 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
249 list<dag> Pattern = [];
252 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
254 class BRK_MMR6_DESC : BRK_FT<"break">;
256 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
257 RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
258 dag OutOperandList = (outs);
259 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
260 string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
261 list<dag> Pattern = [];
262 string DecoderMethod = "DecodeCacheOpMM";
265 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
266 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
268 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
269 : MMR6Arch<instr_asm> {
270 dag OutOperandList = (outs GPROpnd:$rt);
271 dag InOperandList = (ins GPROpnd:$rs);
272 string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
275 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
276 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
278 class EHB_MMR6_DESC : Barrier<"ehb">;
279 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
281 class ERET_MMR6_DESC : ER_FT<"eret">;
282 class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
284 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
285 RegisterOperand GPROpnd>
287 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
288 string AsmString = !strconcat(opstr, "\t$rt, $offset");
289 list<dag> Pattern = [];
290 bit isTerminator = 1;
291 bit hasDelaySlot = 0;
294 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
297 list<Register> Defs = [RA];
300 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
303 list<Register> Defs = [AT];
306 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
307 Operand ImmOpnd> : MMR6Arch<instr_asm> {
308 dag OutOperandList = (outs GPROpnd:$rd);
309 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
310 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
311 list<dag> Pattern = [];
314 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
316 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
317 : MMR6Arch<instr_asm> {
318 dag OutOperandList = (outs GPROpnd:$rt);
319 dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
320 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
321 list<dag> Pattern = [];
324 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
326 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
327 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
328 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
329 : MMR6Arch<instr_asm> {
330 dag OutOperandList = (outs GPROpnd:$rt);
331 dag InOperandList = (ins simm16:$imm);
332 string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
333 list<dag> Pattern = [];
336 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
337 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
339 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
340 Operand ImmOpnd> : MMR6Arch<instr_asm> {
341 dag OutOperandList = (outs GPROpnd:$rd);
342 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
343 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
344 list<dag> Pattern = [];
347 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2>;
349 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
350 Operand ImmOpnd> : MMR6Arch<instr_asm> {
351 dag OutOperandList = (outs GPROpnd:$rt);
352 dag InOperandList = (ins ImmOpnd:$imm);
353 string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
354 list<dag> Pattern = [];
357 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
358 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
360 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
361 : MMR6Arch<instr_asm> {
362 dag OutOperandList = (outs GPROpnd:$rd);
363 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
364 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
365 list<dag> Pattern = [];
368 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
369 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
370 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
371 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
372 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
373 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
374 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
375 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
376 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
377 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
378 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
379 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
380 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
381 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
383 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
384 SDPatternOperator OpNode = null_frag,
385 InstrItinClass Itin = NoItinerary,
386 ComplexPattern Addr = addr> :
387 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
388 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
389 let DecoderMethod = "DecodeMem";
392 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
393 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9gpr>;
395 /// Floating Point Instructions
396 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
397 InstrItinClass Itin, bit isComm,
398 SDPatternOperator OpNode = null_frag> : HARDFLOAT {
399 dag OutOperandList = (outs RC:$fd);
400 dag InOperandList = (ins RC:$ft, RC:$fs);
401 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
402 list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
403 InstrItinClass Itinerary = Itin;
404 bit isCommutable = isComm;
406 class FADD_S_MMR6_DESC
407 : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
408 class FADD_D_MMR6_DESC
409 : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
410 class FSUB_S_MMR6_DESC
411 : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
412 class FSUB_D_MMR6_DESC
413 : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
414 class FMUL_S_MMR6_DESC
415 : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
416 class FMUL_D_MMR6_DESC
417 : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
418 class FDIV_S_MMR6_DESC
419 : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
420 class FDIV_D_MMR6_DESC
421 : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
422 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
423 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
424 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
425 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
427 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
428 RegisterOperand SrcRC, InstrItinClass Itin,
429 SDPatternOperator OpNode = null_frag>
430 : HARDFLOAT, NeverHasSideEffects {
431 dag OutOperandList = (outs DstRC:$ft);
432 dag InOperandList = (ins SrcRC:$fs);
433 string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
434 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
435 InstrItinClass Itinerary = Itin;
438 class FMOV_S_MMR6_DESC
439 : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
440 class FMOV_D_MMR6_DESC
441 : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
442 class FNEG_S_MMR6_DESC
443 : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
444 class FNEG_D_MMR6_DESC
445 : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
447 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT;
448 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT;
449 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT;
450 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT;
452 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT;
453 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT;
454 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT;
455 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT;
457 class CVT_MMR6_DESC_BASE<
458 string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
459 InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
460 : HARDFLOAT, NeverHasSideEffects {
461 dag OutOperandList = (outs DstRC:$ft);
462 dag InOperandList = (ins SrcRC:$fs);
463 string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
464 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
465 InstrItinClass Itinerary = Itin;
469 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
471 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
473 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
475 class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
477 class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
479 class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
481 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
483 class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
485 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
487 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
490 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
491 RegisterOperand FGROpnd> {
492 def CMP_AF_#NAME : POOL32F_CMP_FM<
493 !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
494 CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
496 def CMP_UN_#NAME : POOL32F_CMP_FM<
497 !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
498 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
500 def CMP_EQ_#NAME : POOL32F_CMP_FM<
501 !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
502 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
504 def CMP_UEQ_#NAME : POOL32F_CMP_FM<
505 !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
506 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
508 def CMP_LT_#NAME : POOL32F_CMP_FM<
509 !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
510 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
512 def CMP_ULT_#NAME : POOL32F_CMP_FM<
513 !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
514 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
516 def CMP_LE_#NAME : POOL32F_CMP_FM<
517 !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
518 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
520 def CMP_ULE_#NAME : POOL32F_CMP_FM<
521 !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
522 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
524 def CMP_SAF_#NAME : POOL32F_CMP_FM<
525 !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
526 CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
528 def CMP_SUN_#NAME : POOL32F_CMP_FM<
529 !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
530 CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
532 def CMP_SEQ_#NAME : POOL32F_CMP_FM<
533 !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
534 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
536 def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
537 !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
538 CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
540 def CMP_SLT_#NAME : POOL32F_CMP_FM<
541 !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
542 CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
544 def CMP_SULT_#NAME : POOL32F_CMP_FM<
545 !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
546 CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
548 def CMP_SLE_#NAME : POOL32F_CMP_FM<
549 !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
550 CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
552 def CMP_SULE_#NAME : POOL32F_CMP_FM<
553 !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
554 CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
558 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
559 RegisterOperand SrcRC, InstrItinClass Itin,
560 SDPatternOperator OpNode = null_frag>
561 : HARDFLOAT, NeverHasSideEffects {
562 dag OutOperandList = (outs DstRC:$ft);
563 dag InOperandList = (ins SrcRC:$fs);
564 string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
565 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
566 InstrItinClass Itinerary = Itin;
568 list<Predicate> EncodingPredicates = [HasStdEnc];
571 class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd,
573 class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd,
575 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
576 FGR32Opnd, II_FLOOR>;
577 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
578 FGR64Opnd, II_FLOOR>;
579 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
580 FGR32Opnd, II_FLOOR>;
581 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
582 AFGR64Opnd, II_FLOOR>;
583 class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
585 class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
587 class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
589 class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
590 AFGR64Opnd, II_CEIL>;
591 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
592 FGR32Opnd, II_TRUNC>;
593 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
594 FGR64Opnd, II_TRUNC>;
595 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
596 FGR32Opnd, II_TRUNC>;
597 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
598 AFGR64Opnd, II_TRUNC>;
599 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
601 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
603 class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
604 FGR32Opnd, II_TRUNC>;
605 class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
606 AFGR64Opnd, II_TRUNC>;
608 //===----------------------------------------------------------------------===//
610 // Instruction Definitions
612 //===----------------------------------------------------------------------===//
614 let DecoderNamespace = "MicroMipsR6" in {
615 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
616 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
617 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
618 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
620 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
622 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
623 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
624 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
625 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
626 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
627 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
628 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
629 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
630 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
632 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
634 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
636 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
638 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
640 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
642 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
644 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
646 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
648 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
649 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
650 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
651 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
652 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
653 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
654 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
655 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
656 def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
657 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
659 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
660 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
661 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
662 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
663 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
664 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
665 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
666 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
667 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
668 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
669 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
670 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
671 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
672 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
673 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
674 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
675 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
677 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
679 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
680 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
681 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
682 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
683 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
684 let DecoderMethod = "DecodeMemMMImm16" in {
685 def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
687 let DecoderMethod = "DecodeMemMMImm9" in {
688 def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
690 /// Floating Point Instructions
691 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
693 def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
695 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
697 def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
699 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
701 def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
703 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
705 def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
707 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
709 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
711 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
713 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
715 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
717 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
719 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
721 def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
723 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
724 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
725 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
726 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
727 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
729 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
731 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
733 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
735 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
737 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
739 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
741 def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
743 def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
745 def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
747 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
749 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
751 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
753 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
755 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
756 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
757 def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
758 def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
759 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
761 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
763 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
765 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
767 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
769 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
771 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
773 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
775 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
777 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
779 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
781 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
783 def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
785 def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
787 def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
789 def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
793 //===----------------------------------------------------------------------===//
795 // MicroMips instruction aliases
797 //===----------------------------------------------------------------------===//
799 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
800 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
801 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
802 !strconcat("b", "\t$offset")>,