1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes microMIPSr6 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
16 // Instruction Encodings
18 //===----------------------------------------------------------------------===//
19 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
20 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
21 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
22 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
23 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
24 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
25 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
26 class AUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11110>;
27 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
28 class AUI_MMR6_ENC : AUI_FM_MMR6;
29 class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>;
30 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
31 class BC16_MMR6_ENC : BC16_FM_MM16R6;
32 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
33 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
34 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
35 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
36 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011101>;
37 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b011111>;
38 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b111000>;
39 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b111000>;
40 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<0b110000>;
41 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<0b110000>;
42 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
43 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
44 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
45 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
46 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
47 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
48 class EI_MMR6_ENC : EIDI_MMR6_ENC<"ei", 0x15d>;
49 class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">;
50 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
51 class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
52 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
53 class JIC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101000>;
54 class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
55 class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
56 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
57 class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>;
58 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
59 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
60 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
61 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
62 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
63 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
64 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
65 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
66 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
67 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
68 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
69 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
70 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
71 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
72 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
73 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
74 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
75 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
76 class SWE_MMR6_ENC : POOL32C_SWE_FM_MMR6<"swe", 0x18, 0xa, 0x7>;
77 class PREFE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b010>;
78 class CACHEE_MMR6_ENC : POOL32C_ST_EVA_FM_MMR6<0b011000, 0b011>;
79 class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x3c5>;
80 class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x1ec>;
81 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
82 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
83 class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
84 class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
85 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
86 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
87 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
88 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
89 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
90 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
91 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
92 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
93 class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
94 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
95 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
96 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
97 class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
98 class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
99 class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
100 class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
101 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
102 class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
103 class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
104 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
105 class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
106 class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
107 class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
108 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
109 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
111 class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
112 class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
113 class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16;
114 class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
115 class OR16_MMR6_ENC : POOL16C_OR16_FM_MMR6;
116 class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
117 class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
119 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
120 RegisterOperand GPROpnd>
121 : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
122 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
123 dag OutOperandList = (outs);
124 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
125 list<Register> Defs = [AT];
128 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
130 list<Register> Defs = [RA];
133 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
135 list<Register> Defs = [RA];
138 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
140 list<Register> Defs = [RA];
143 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
145 list<Register> Defs = [RA];
148 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
150 list<Register> Defs = [RA];
153 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
155 list<Register> Defs = [RA];
158 /// Floating Point Instructions
159 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
160 class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
161 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
162 class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
163 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
164 class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
165 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
166 class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
167 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
168 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
169 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
170 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
171 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
172 class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
173 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
174 class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
175 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
176 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
177 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
178 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
179 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
180 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
181 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
182 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
184 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
185 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
186 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
187 class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>;
188 class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>;
189 class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>;
190 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
191 class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>;
192 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
193 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
195 //===----------------------------------------------------------------------===//
197 // Instruction Descriptions
199 //===----------------------------------------------------------------------===//
201 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
202 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
203 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
204 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
205 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
206 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
207 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
209 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
210 : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
211 dag InOperandList = (ins opnd:$offset);
212 dag OutOperandList = (outs);
213 string AsmString = !strconcat(instr_asm, "\t$offset");
217 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
219 list<Register> Defs = [RA];
221 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
223 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
224 !strconcat("bc16", "\t$offset"), [],
226 MMR6Arch<"bc16">, MicroMipsR6Inst16 {
228 let isTerminator = 1;
230 let hasDelaySlot = 0;
231 let AdditionalPredicates = [RelocPIC];
235 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
236 : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>, MMR6Arch<instr_asm> {
238 let isTerminator = 1;
239 let hasDelaySlot = 0;
242 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
243 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
245 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>;
246 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>;
248 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
249 : MMR6Arch<instr_asm> {
250 dag OutOperandList = (outs GPROpnd:$rd);
251 dag InOperandList = (ins GPROpnd:$rt);
252 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
253 list<dag> Pattern = [];
256 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
258 class BRK_MMR6_DESC : BRK_FT<"break">;
260 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
261 RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
262 dag OutOperandList = (outs);
263 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
264 string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
265 list<dag> Pattern = [];
266 string DecoderMethod = "DecodeCacheOpMM";
269 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
270 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
272 class PREFE_CACHEE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
273 RegisterOperand GPROpnd> :
274 CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd,
276 string DecoderMethod = "DecodePrefeOpMM";
279 class PREFE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"prefe", mem_mm_9, GPR32Opnd>;
280 class CACHEE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"cachee", mem_mm_9, GPR32Opnd>;
282 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
283 : MMR6Arch<instr_asm> {
284 dag OutOperandList = (outs GPROpnd:$rt);
285 dag InOperandList = (ins GPROpnd:$rs);
286 string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
289 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
290 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
292 class EHB_MMR6_DESC : Barrier<"ehb">;
293 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
295 class ERET_MMR6_DESC : ER_FT<"eret">;
296 class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
298 class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
299 : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
300 [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
301 MMR6Arch<opstr>, MicroMipsR6Inst16 {
303 let hasDelaySlot = 0;
306 class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
308 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
309 RegisterOperand GPROpnd>
311 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
312 string AsmString = !strconcat(opstr, "\t$rt, $offset");
313 list<dag> Pattern = [];
314 bit isTerminator = 1;
315 bit hasDelaySlot = 0;
318 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
321 list<Register> Defs = [RA];
324 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
327 list<Register> Defs = [AT];
330 class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
331 : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
333 MMR6Arch<opstr>, MicroMipsR6Inst16 {
334 let hasDelaySlot = 0;
336 let isIndirectBranch = 1;
338 class JRC16_MMR6_DESC : JRC16_MMR6_DESC_BASE<"jrc16", GPR32Opnd>;
340 class JRCADDIUSP_MMR6_DESC
341 : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm",
342 [], II_JRADDIUSP, FrmR>,
343 MMR6Arch<"jrcaddiusp">, MicroMipsR6Inst16 {
344 let hasDelaySlot = 0;
345 let isTerminator = 1;
348 let isIndirectBranch = 1;
351 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
352 Operand ImmOpnd> : MMR6Arch<instr_asm> {
353 dag OutOperandList = (outs GPROpnd:$rd);
354 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
355 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
356 list<dag> Pattern = [];
359 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
361 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
362 : MMR6Arch<instr_asm> {
363 dag OutOperandList = (outs GPROpnd:$rt);
364 dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
365 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
366 list<dag> Pattern = [];
369 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
371 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
372 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;
373 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
374 : MMR6Arch<instr_asm> {
375 dag OutOperandList = (outs GPROpnd:$rt);
376 dag InOperandList = (ins simm16:$imm);
377 string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
378 list<dag> Pattern = [];
381 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
382 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
384 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
385 Operand ImmOpnd> : MMR6Arch<instr_asm> {
386 dag OutOperandList = (outs GPROpnd:$rd);
387 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
388 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
389 list<dag> Pattern = [];
392 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2>;
394 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
395 Operand ImmOpnd> : MMR6Arch<instr_asm> {
396 dag OutOperandList = (outs GPROpnd:$rt);
397 dag InOperandList = (ins ImmOpnd:$imm);
398 string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
399 list<dag> Pattern = [];
402 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
403 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
405 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
406 : MMR6Arch<instr_asm> {
407 dag OutOperandList = (outs GPROpnd:$rd);
408 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
409 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
410 list<dag> Pattern = [];
413 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
414 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
415 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
416 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
417 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
418 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
419 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
420 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
421 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
422 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
423 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
424 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
425 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
426 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
428 class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
429 SDPatternOperator OpNode = null_frag,
430 InstrItinClass Itin = NoItinerary,
431 ComplexPattern Addr = addr> :
432 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
433 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
434 let DecoderMethod = "DecodeMem";
437 class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
438 class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9>;
440 class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
441 : MMR6Arch<instr_asm> {
442 dag InOperandList = (ins RO:$rs);
443 dag OutOperandList = (outs RO:$rt);
444 string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
445 list<dag> Pattern = [];
447 string BaseOpcode = instr_asm;
448 bit hasSideEffects = 0;
450 class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd>;
451 class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd>;
453 /// Floating Point Instructions
454 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
455 InstrItinClass Itin, bit isComm,
456 SDPatternOperator OpNode = null_frag> : HARDFLOAT {
457 dag OutOperandList = (outs RC:$fd);
458 dag InOperandList = (ins RC:$ft, RC:$fs);
459 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
460 list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
461 InstrItinClass Itinerary = Itin;
462 bit isCommutable = isComm;
464 class FADD_S_MMR6_DESC
465 : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
466 class FADD_D_MMR6_DESC
467 : FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
468 class FSUB_S_MMR6_DESC
469 : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
470 class FSUB_D_MMR6_DESC
471 : FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
472 class FMUL_S_MMR6_DESC
473 : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
474 class FMUL_D_MMR6_DESC
475 : FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
476 class FDIV_S_MMR6_DESC
477 : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
478 class FDIV_D_MMR6_DESC
479 : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
480 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
481 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
482 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
483 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
485 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
486 RegisterOperand SrcRC, InstrItinClass Itin,
487 SDPatternOperator OpNode = null_frag>
488 : HARDFLOAT, NeverHasSideEffects {
489 dag OutOperandList = (outs DstRC:$ft);
490 dag InOperandList = (ins SrcRC:$fs);
491 string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
492 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
493 InstrItinClass Itinerary = Itin;
496 class FMOV_S_MMR6_DESC
497 : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
498 class FMOV_D_MMR6_DESC
499 : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
500 class FNEG_S_MMR6_DESC
501 : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
502 class FNEG_D_MMR6_DESC
503 : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
505 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT;
506 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT;
507 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT;
508 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT;
510 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT;
511 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT;
512 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT;
513 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT;
515 class CVT_MMR6_DESC_BASE<
516 string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
517 InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
518 : HARDFLOAT, NeverHasSideEffects {
519 dag OutOperandList = (outs DstRC:$ft);
520 dag InOperandList = (ins SrcRC:$fs);
521 string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
522 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
523 InstrItinClass Itinerary = Itin;
527 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
529 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
531 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
533 class CVT_W_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.d", FGR32Opnd, AFGR64Opnd,
535 class CVT_D_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.s", FGR32Opnd, AFGR64Opnd,
537 class CVT_D_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.w", FGR32Opnd, AFGR64Opnd,
539 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
541 class CVT_S_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.d", AFGR64Opnd, FGR32Opnd,
543 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
545 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
548 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
549 RegisterOperand FGROpnd> {
550 def CMP_AF_#NAME : POOL32F_CMP_FM<
551 !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
552 CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
554 def CMP_UN_#NAME : POOL32F_CMP_FM<
555 !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
556 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
558 def CMP_EQ_#NAME : POOL32F_CMP_FM<
559 !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
560 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
562 def CMP_UEQ_#NAME : POOL32F_CMP_FM<
563 !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
564 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
566 def CMP_LT_#NAME : POOL32F_CMP_FM<
567 !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
568 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
570 def CMP_ULT_#NAME : POOL32F_CMP_FM<
571 !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
572 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
574 def CMP_LE_#NAME : POOL32F_CMP_FM<
575 !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
576 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
578 def CMP_ULE_#NAME : POOL32F_CMP_FM<
579 !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
580 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
582 def CMP_SAF_#NAME : POOL32F_CMP_FM<
583 !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
584 CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
586 def CMP_SUN_#NAME : POOL32F_CMP_FM<
587 !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
588 CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
590 def CMP_SEQ_#NAME : POOL32F_CMP_FM<
591 !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
592 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
594 def CMP_SUEQ_#NAME : POOL32F_CMP_FM<
595 !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
596 CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
598 def CMP_SLT_#NAME : POOL32F_CMP_FM<
599 !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
600 CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
602 def CMP_SULT_#NAME : POOL32F_CMP_FM<
603 !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
604 CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
606 def CMP_SLE_#NAME : POOL32F_CMP_FM<
607 !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
608 CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
610 def CMP_SULE_#NAME : POOL32F_CMP_FM<
611 !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
612 CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, R6MMR6Rel,
616 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
617 RegisterOperand SrcRC, InstrItinClass Itin,
618 SDPatternOperator OpNode = null_frag>
619 : HARDFLOAT, NeverHasSideEffects {
620 dag OutOperandList = (outs DstRC:$ft);
621 dag InOperandList = (ins SrcRC:$fs);
622 string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
623 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
624 InstrItinClass Itinerary = Itin;
626 list<Predicate> EncodingPredicates = [HasStdEnc];
629 class ABS_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd,
631 class ABS_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd,
633 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
634 FGR32Opnd, II_FLOOR>;
635 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
636 FGR64Opnd, II_FLOOR>;
637 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
638 FGR32Opnd, II_FLOOR>;
639 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
640 AFGR64Opnd, II_FLOOR>;
641 class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
643 class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
645 class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
647 class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
648 AFGR64Opnd, II_CEIL>;
649 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
650 FGR32Opnd, II_TRUNC>;
651 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
652 FGR64Opnd, II_TRUNC>;
653 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
654 FGR32Opnd, II_TRUNC>;
655 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
656 AFGR64Opnd, II_TRUNC>;
657 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
659 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
661 class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
662 FGR32Opnd, II_TRUNC>;
663 class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
664 AFGR64Opnd, II_TRUNC>;
666 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO>
667 : Store<opstr, RO>, MMR6Arch<opstr> {
668 let DecoderMethod = "DecodeMemMMImm16";
670 class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>;
672 class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
673 : MMR6Arch<instr_asm>, MipsR6Inst {
674 dag OutOperandList = (outs);
675 dag InOperandList = (ins RO:$rt, mem_mm_9:$addr);
676 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
677 string DecoderMethod = "DecodeStoreEvaOpMM";
680 class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd>;
681 class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>;
682 class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>;
683 class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>;
685 class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
686 MMR6Arch<instr_asm>, MipsR6Inst {
687 dag OutOperandList = (outs RO:$rt);
688 dag InOperandList = (ins mem_mm_12:$addr);
689 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
690 string DecoderMethod = "DecodeMemMMImm9";
693 class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
694 class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
695 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
697 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
699 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
701 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">;
702 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
704 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
706 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
709 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
710 dag OutOperandList = (outs GPR32Opnd:$rt);
711 dag InOperandList = (ins mem:$addr);
712 string AsmString = "lw\t$rt, $addr";
713 let DecoderMethod = "DecodeMemMMImm16";
714 let canFoldAsLoad = 1;
716 list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
717 InstrItinClass Itinerary = II_LW;
720 class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
721 dag OutOperandList = (outs GPR32Opnd:$rt);
722 dag InOperandList = (ins uimm16:$imm16);
723 string AsmString = "lui\t$rt, $imm16";
724 list<dag> Pattern = [];
725 bit hasSideEffects = 0;
726 bit isReMaterializable = 1;
727 InstrItinClass Itinerary = II_LUI;
731 //===----------------------------------------------------------------------===//
733 // Instruction Definitions
735 //===----------------------------------------------------------------------===//
737 let DecoderNamespace = "MicroMipsR6" in {
738 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
739 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
740 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
741 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
743 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
745 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
746 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
747 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
748 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
749 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
750 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
751 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
752 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
753 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
755 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
757 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
759 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
761 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
763 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
765 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
767 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
769 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
771 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
772 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
773 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
774 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
775 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
776 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
777 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
778 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
779 def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
780 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
782 def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
784 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
785 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
786 def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
787 def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
789 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
790 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
791 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
792 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
793 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
794 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
795 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
796 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
797 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
798 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
799 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
800 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
801 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
802 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
803 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
805 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
807 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
808 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
809 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
810 def PREFE_MMR6 : StdMMR6Rel, PREFE_MMR6_ENC, PREFE_MMR6_DESC, ISA_MICROMIPS32R6;
811 def CACHEE_MMR6 : StdMMR6Rel, CACHEE_MMR6_ENC, CACHEE_MMR6_DESC,
813 def WRPGPR_MMR6 : StdMMR6Rel, WRPGPR_MMR6_ENC, WRPGPR_MMR6_DESC,
815 def WSBH_MMR6 : StdMMR6Rel, WSBH_MMR6_ENC, WSBH_MMR6_DESC, ISA_MICROMIPS32R6;
816 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
817 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
818 let DecoderMethod = "DecodeMemMMImm16" in {
819 def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
821 let DecoderMethod = "DecodeMemMMImm9" in {
822 def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
824 /// Floating Point Instructions
825 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
827 def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
829 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
831 def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
833 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
835 def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
837 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
839 def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
841 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
843 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
845 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
847 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
849 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
851 def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
853 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
855 def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
857 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
858 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
859 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
860 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
861 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
863 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
865 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
867 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
869 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
871 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
873 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
875 def CVT_W_D_MMR6 : StdMMR6Rel, CVT_W_D_MMR6_ENC, CVT_W_D_MMR6_DESC,
877 def CVT_D_S_MMR6 : StdMMR6Rel, CVT_D_S_MMR6_ENC, CVT_D_S_MMR6_DESC,
879 def CVT_D_W_MMR6 : StdMMR6Rel, CVT_D_W_MMR6_ENC, CVT_D_W_MMR6_DESC,
881 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
883 def CVT_S_D_MMR6 : StdMMR6Rel, CVT_S_D_MMR6_ENC, CVT_S_D_MMR6_DESC,
885 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
887 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
889 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
890 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
891 def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6;
892 def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6;
893 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
895 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
897 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
899 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
901 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
903 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
905 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
907 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
909 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
911 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
913 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
915 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
917 def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
919 def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
921 def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
923 def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
925 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
926 def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
927 def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
928 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
929 def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
930 def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6;
931 def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6;
932 def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
933 def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
935 def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
937 def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
939 def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
941 def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
943 def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
945 def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
947 def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
951 //===----------------------------------------------------------------------===//
953 // MicroMips instruction aliases
955 //===----------------------------------------------------------------------===//
957 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
958 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
959 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
960 !strconcat("b", "\t$offset")> {
961 string DecoderNamespace = "MicroMipsR6";