1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
3 def simm12 : Operand<i32> {
4 let DecoderMethod = "DecodeSimm12";
7 def mem_mm_12 : Operand<i32> {
8 let PrintMethod = "printMemOperand";
9 let MIOperandInfo = (ops GPR32, simm12);
10 let EncoderMethod = "getMemEncodingMMImm12";
11 let ParserMatchClass = MipsMemAsmOperand;
12 let OperandType = "OPERAND_MEMORY";
15 def jmptarget_mm : Operand<OtherVT> {
16 let EncoderMethod = "getJumpTargetOpValueMM";
19 def calltarget_mm : Operand<iPTR> {
20 let EncoderMethod = "getJumpTargetOpValueMM";
23 def brtarget_mm : Operand<OtherVT> {
24 let EncoderMethod = "getBranchTargetOpValueMM";
25 let OperandType = "OPERAND_PCREL";
26 let DecoderMethod = "DecodeBranchTargetMM";
29 let canFoldAsLoad = 1 in
30 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
32 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
33 !strconcat(opstr, "\t$rt, $addr"),
34 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
36 let DecoderMethod = "DecodeMemMMImm12";
37 string Constraints = "$src = $rt";
40 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
42 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
43 !strconcat(opstr, "\t$rt, $addr"),
44 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
45 let DecoderMethod = "DecodeMemMMImm12";
48 class LLBaseMM<string opstr, RegisterOperand RO> :
49 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
50 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
51 let DecoderMethod = "DecodeMem";
55 class SCBaseMM<string opstr, RegisterOperand RO> :
56 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
57 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
58 let DecoderMethod = "DecodeMem";
60 let Constraints = "$rt = $dst";
63 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
64 /// Arithmetic Instructions (ALU Immediate)
65 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
67 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
69 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
71 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
73 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
75 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
77 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
79 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
81 /// Arithmetic Instructions (3-Operand, R-Type)
82 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
83 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
84 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
85 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
86 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
87 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
88 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
90 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IIAlu, and>,
92 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IIAlu, or>,
94 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IIAlu, xor>,
96 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
97 def MULT_MM : MMRel, Mult<"mult", IIImul, GPR32Opnd, [HI0, LO0]>,
99 def MULTu_MM : MMRel, Mult<"multu", IIImul, GPR32Opnd, [HI0, LO0]>,
101 def SDIV_MM : MMRel, Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>,
103 def UDIV_MM : MMRel, Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>,
106 /// Shift Instructions
107 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd>,
109 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd>,
111 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd>,
113 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd>,
115 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd>,
117 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd>,
119 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd>,
121 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd>,
124 /// Load and Store Instructions - aligned
125 let DecoderMethod = "DecodeMemMMImm16" in {
126 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
127 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
128 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
129 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
130 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
131 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
132 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
133 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
136 /// Load and Store Instructions - unaligned
137 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
139 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
141 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
143 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
147 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
148 NoItinerary>, ADD_FM_MM<0, 0x58>;
149 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
150 NoItinerary>, ADD_FM_MM<0, 0x18>;
151 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, IIAlu>,
152 CMov_F_I_FM_MM<0x25>;
153 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, IIAlu>,
156 /// Move to/from HI/LO
157 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
159 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
161 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
163 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
166 /// Multiply Add/Sub Instructions
167 def MADD_MM : MMRel, MArithR<"madd", 1>, MULT_FM_MM<0x32c>;
168 def MADDU_MM : MMRel, MArithR<"maddu", 1>, MULT_FM_MM<0x36c>;
169 def MSUB_MM : MMRel, MArithR<"msub">, MULT_FM_MM<0x3ac>;
170 def MSUBU_MM : MMRel, MArithR<"msubu">, MULT_FM_MM<0x3ec>;
173 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>;
174 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>;
176 /// Sign Ext In Register Instructions.
177 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM_MM<0x0ac>;
178 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM_MM<0x0ec>;
180 /// Word Swap Bytes Within Halfwords
181 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>;
183 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
185 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
188 /// Jump Instructions
189 let DecoderMethod = "DecodeJumpTargetMM" in {
190 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
192 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
194 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
195 def JALR_MM : MMRel, JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
196 def RET_MM : MMRel, RetBase<"ret", GPR32Opnd>, JR_FM_MM<0x3c>;
198 /// Branch Instructions
199 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
201 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
203 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
205 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
207 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
209 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
211 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
213 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
216 /// Control Instructions
217 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
218 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
219 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
220 def WAIT_MM : MMRel, WAIT_FT<"wait">, WAIT_FM_MM;
221 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
222 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
223 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>;
224 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>;
226 /// Trap Instructions
227 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
228 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
229 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
230 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
231 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
232 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
234 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
235 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
236 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
237 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
238 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
239 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
241 /// Load-linked, Store-conditional
242 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
243 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;