1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
3 def simm4 : Operand<i32>;
5 def simm12 : Operand<i32> {
6 let DecoderMethod = "DecodeSimm12";
9 def uimm5_lsl2 : Operand<OtherVT> {
10 let EncoderMethod = "getUImm5Lsl2Encoding";
13 def mem_mm_12 : Operand<i32> {
14 let PrintMethod = "printMemOperand";
15 let MIOperandInfo = (ops GPR32, simm12);
16 let EncoderMethod = "getMemEncodingMMImm12";
17 let ParserMatchClass = MipsMemAsmOperand;
18 let OperandType = "OPERAND_MEMORY";
21 def jmptarget_mm : Operand<OtherVT> {
22 let EncoderMethod = "getJumpTargetOpValueMM";
25 def calltarget_mm : Operand<iPTR> {
26 let EncoderMethod = "getJumpTargetOpValueMM";
29 def brtarget_mm : Operand<OtherVT> {
30 let EncoderMethod = "getBranchTargetOpValueMM";
31 let OperandType = "OPERAND_PCREL";
32 let DecoderMethod = "DecodeBranchTargetMM";
35 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
37 InstSE<(outs), (ins RO:$rs, opnd:$offset),
38 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
45 let canFoldAsLoad = 1 in
46 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
48 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
49 !strconcat(opstr, "\t$rt, $addr"),
50 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
52 let DecoderMethod = "DecodeMemMMImm12";
53 string Constraints = "$src = $rt";
56 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
58 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
59 !strconcat(opstr, "\t$rt, $addr"),
60 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
61 let DecoderMethod = "DecodeMemMMImm12";
64 class LLBaseMM<string opstr, RegisterOperand RO> :
65 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
66 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
67 let DecoderMethod = "DecodeMemMMImm12";
71 class SCBaseMM<string opstr, RegisterOperand RO> :
72 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
73 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
74 let DecoderMethod = "DecodeMemMMImm12";
76 let Constraints = "$rt = $dst";
79 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
80 InstrItinClass Itin = NoItinerary> :
81 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
82 !strconcat(opstr, "\t$rt, $addr"),
83 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
84 let DecoderMethod = "DecodeMemMMImm12";
85 let canFoldAsLoad = 1;
89 class AddImmUS5<string opstr, RegisterOperand RO> :
90 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
91 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
92 let Constraints = "$rd = $dst";
96 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
97 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
98 [], II_MFHI_MFLO, FrmR> {
100 let hasSideEffects = 0;
103 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
104 InstrItinClass Itin = NoItinerary> :
105 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
106 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
107 let isCommutable = isComm;
108 let isReMaterializable = 1;
111 // 16-bit Jump and Link (Call)
112 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
113 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
114 [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
116 let hasDelaySlot = 1;
120 // Base class for JRADDIUSP instruction.
121 class JumpRAddiuStackMM16 :
122 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
123 [], IIBranch, FrmR> {
124 let isTerminator = 1;
126 let hasDelaySlot = 1;
128 let isIndirectBranch = 1;
131 // 16-bit Jump and Link (Call) - Short Delay Slot
132 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
133 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
134 [], IIBranch, FrmR> {
136 let hasDelaySlot = 1;
140 // 16-bit Jump Register Compact - No delay slot
141 class JumpRegCMM16<string opstr, RegisterOperand RO> :
142 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
143 [], IIBranch, FrmR> {
144 let isTerminator = 1;
147 let isIndirectBranch = 1;
150 // MicroMIPS Jump and Link (Call) - Short Delay Slot
151 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
152 class JumpLinkMM<string opstr, DAGOperand opnd> :
153 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
154 [], IIBranch, FrmJ, opstr> {
155 let DecoderMethod = "DecodeJumpTargetMM";
158 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
159 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
162 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
163 RegisterOperand RO> :
164 InstSE<(outs), (ins RO:$rs, opnd:$offset),
165 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
168 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
169 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
170 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
171 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
172 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
173 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
174 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
175 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
177 class WaitMM<string opstr> :
178 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
179 NoItinerary, FrmOther, opstr>;
181 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
182 /// Compact Branch Instructions
183 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
184 COMPACT_BRANCH_FM_MM<0x7>;
185 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
186 COMPACT_BRANCH_FM_MM<0x5>;
188 /// Arithmetic Instructions (ALU Immediate)
189 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
191 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
193 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
195 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
197 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
199 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
201 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
203 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
205 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
208 /// Arithmetic Instructions (3-Operand, R-Type)
209 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
210 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
211 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
212 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
213 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
214 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
215 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
217 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
219 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
221 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
223 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
224 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
226 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
228 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
230 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
233 /// Shift Instructions
234 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
236 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
238 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
240 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
242 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
244 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
246 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
248 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
251 /// Load and Store Instructions - aligned
252 let DecoderMethod = "DecodeMemMMImm16" in {
253 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
254 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
255 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
256 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
257 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
258 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
259 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
260 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
263 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
265 /// Load and Store Instructions - unaligned
266 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
268 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
270 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
272 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
276 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
277 NoItinerary>, ADD_FM_MM<0, 0x58>;
278 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
279 NoItinerary>, ADD_FM_MM<0, 0x18>;
280 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
281 CMov_F_I_FM_MM<0x25>;
282 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
285 /// Move to/from HI/LO
286 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
288 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
290 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
292 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
295 /// Multiply Add/Sub Instructions
296 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
297 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
298 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
299 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
302 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
304 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
307 /// Sign Ext In Register Instructions.
308 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
309 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
310 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
311 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
313 /// Word Swap Bytes Within Halfwords
314 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,
317 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
319 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
322 /// Jump Instructions
323 let DecoderMethod = "DecodeJumpTargetMM" in {
324 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
326 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
328 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
329 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
331 /// Jump Instructions - Short Delay Slot
332 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
333 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
335 /// Branch Instructions
336 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
338 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
340 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
342 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
344 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
346 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
348 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
350 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
353 /// Branch Instructions - Short Delay Slot
354 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
355 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
356 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
357 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
359 /// Control Instructions
360 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
361 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
362 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
363 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
364 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
365 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
366 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
368 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
371 /// Trap Instructions
372 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
373 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
374 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
375 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
376 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
377 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
379 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
380 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
381 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
382 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
383 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
384 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
386 /// Load-linked, Store-conditional
387 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
388 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
390 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
391 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
392 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
393 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
396 //===----------------------------------------------------------------------===//
397 // MicroMips instruction aliases
398 //===----------------------------------------------------------------------===//
400 let Predicates = [InMicroMips] in {
401 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;