1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
3 def simm4 : Operand<i32> {
4 let DecoderMethod = "DecodeSimm4";
6 def li_simm7 : Operand<i32> {
7 let DecoderMethod = "DecodeLiSimm7";
10 def simm12 : Operand<i32> {
11 let DecoderMethod = "DecodeSimm12";
14 def uimm5_lsl2 : Operand<OtherVT> {
15 let EncoderMethod = "getUImm5Lsl2Encoding";
16 let DecoderMethod = "DecodeUImm5lsl2";
19 def uimm6_lsl2 : Operand<i32> {
20 let EncoderMethod = "getUImm6Lsl2Encoding";
21 let DecoderMethod = "DecodeUImm6Lsl2";
24 def simm9_addiusp : Operand<i32> {
25 let EncoderMethod = "getSImm9AddiuspValue";
26 let DecoderMethod = "DecodeSimm9SP";
29 def uimm3_shift : Operand<i32> {
30 let EncoderMethod = "getUImm3Mod8Encoding";
33 def simm3_lsa2 : Operand<i32> {
34 let EncoderMethod = "getSImm3Lsa2Value";
35 let DecoderMethod = "DecodeAddiur2Simm7";
38 def uimm4_andi : Operand<i32> {
39 let EncoderMethod = "getUImm4AndValue";
40 let DecoderMethod = "DecodeANDI16Imm";
43 def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
45 Imm < 28 && Imm > 0);}]>;
47 def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
49 def immZExtAndi16 : ImmLeaf<i32,
50 [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
51 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
52 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
54 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
56 def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
58 def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
59 let Name = "MicroMipsMem";
60 let RenderMethod = "addMicroMipsMemOperands";
61 let ParserMethod = "parseMemOperand";
62 let PredicateMethod = "isMemWithGRPMM16Base";
65 class mem_mm_4_generic : Operand<i32> {
66 let PrintMethod = "printMemOperand";
67 let MIOperandInfo = (ops ptr_rc, simm4);
68 let OperandType = "OPERAND_MEMORY";
69 let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
72 def mem_mm_4 : mem_mm_4_generic {
73 let EncoderMethod = "getMemEncodingMMImm4";
76 def mem_mm_4_lsl1 : mem_mm_4_generic {
77 let EncoderMethod = "getMemEncodingMMImm4Lsl1";
80 def mem_mm_4_lsl2 : mem_mm_4_generic {
81 let EncoderMethod = "getMemEncodingMMImm4Lsl2";
84 def mem_mm_12 : Operand<i32> {
85 let PrintMethod = "printMemOperand";
86 let MIOperandInfo = (ops GPR32, simm12);
87 let EncoderMethod = "getMemEncodingMMImm12";
88 let ParserMatchClass = MipsMemAsmOperand;
89 let OperandType = "OPERAND_MEMORY";
92 def MipsMemUimm4AsmOperand : AsmOperandClass {
93 let Name = "MemOffsetUimm4";
94 let SuperClasses = [MipsMemAsmOperand];
95 let RenderMethod = "addMemOperands";
96 let ParserMethod = "parseMemOperand";
97 let PredicateMethod = "isMemWithUimmOffsetSP<6>";
100 def mem_mm_4sp : Operand<i32> {
101 let PrintMethod = "printMemOperand";
102 let MIOperandInfo = (ops GPR32, uimm8);
103 let EncoderMethod = "getMemEncodingMMImm4sp";
104 let ParserMatchClass = MipsMemUimm4AsmOperand;
105 let OperandType = "OPERAND_MEMORY";
108 def jmptarget_mm : Operand<OtherVT> {
109 let EncoderMethod = "getJumpTargetOpValueMM";
112 def calltarget_mm : Operand<iPTR> {
113 let EncoderMethod = "getJumpTargetOpValueMM";
116 def brtarget_mm : Operand<OtherVT> {
117 let EncoderMethod = "getBranchTargetOpValueMM";
118 let OperandType = "OPERAND_PCREL";
119 let DecoderMethod = "DecodeBranchTargetMM";
122 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
123 RegisterOperand RO> :
124 InstSE<(outs), (ins RO:$rs, opnd:$offset),
125 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
127 let isTerminator = 1;
128 let hasDelaySlot = 0;
132 let canFoldAsLoad = 1 in
133 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
135 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
136 !strconcat(opstr, "\t$rt, $addr"),
137 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
139 let DecoderMethod = "DecodeMemMMImm12";
140 string Constraints = "$src = $rt";
143 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
145 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
146 !strconcat(opstr, "\t$rt, $addr"),
147 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
148 let DecoderMethod = "DecodeMemMMImm12";
151 class LLBaseMM<string opstr, RegisterOperand RO> :
152 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
153 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
154 let DecoderMethod = "DecodeMemMMImm12";
158 class SCBaseMM<string opstr, RegisterOperand RO> :
159 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
160 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
161 let DecoderMethod = "DecodeMemMMImm12";
163 let Constraints = "$rt = $dst";
166 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
167 InstrItinClass Itin = NoItinerary> :
168 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
169 !strconcat(opstr, "\t$rt, $addr"),
170 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
171 let DecoderMethod = "DecodeMemMMImm12";
172 let canFoldAsLoad = 1;
176 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
177 InstrItinClass Itin = NoItinerary,
178 SDPatternOperator OpNode = null_frag> :
179 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
180 !strconcat(opstr, "\t$rd, $rs, $rt"),
181 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
182 let isCommutable = isComm;
185 class AndImmMM16<string opstr, RegisterOperand RO,
186 InstrItinClass Itin = NoItinerary> :
187 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
188 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
190 class LogicRMM16<string opstr, RegisterOperand RO,
191 InstrItinClass Itin = NoItinerary,
192 SDPatternOperator OpNode = null_frag> :
193 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
194 !strconcat(opstr, "\t$rt, $rs"),
195 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
196 let isCommutable = 1;
197 let Constraints = "$rt = $dst";
200 class NotMM16<string opstr, RegisterOperand RO> :
201 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
202 !strconcat(opstr, "\t$rt, $rs"),
203 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
205 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
206 InstrItinClass Itin = NoItinerary> :
207 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
208 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
210 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
211 InstrItinClass Itin, Operand MemOpnd> :
212 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
213 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
214 let DecoderMethod = "DecodeMemMMImm4";
215 let canFoldAsLoad = 1;
219 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
220 SDPatternOperator OpNode, InstrItinClass Itin,
222 MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
223 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
224 let DecoderMethod = "DecodeMemMMImm4";
228 class AddImmUR2<string opstr, RegisterOperand RO> :
229 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
230 !strconcat(opstr, "\t$rd, $rs, $imm"),
231 [], NoItinerary, FrmR> {
232 let isCommutable = 1;
235 class AddImmUS5<string opstr, RegisterOperand RO> :
236 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
237 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
238 let Constraints = "$rd = $dst";
241 class AddImmUR1SP<string opstr, RegisterOperand RO> :
242 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
243 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
245 class AddImmUSP<string opstr> :
246 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
247 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
249 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
250 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
251 [], II_MFHI_MFLO, FrmR> {
253 let hasSideEffects = 0;
256 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
257 InstrItinClass Itin = NoItinerary> :
258 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
259 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
260 let isCommutable = isComm;
261 let isReMaterializable = 1;
264 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
265 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
266 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
267 let isReMaterializable = 1;
270 // 16-bit Jump and Link (Call)
271 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
272 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
273 [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
275 let hasDelaySlot = 1;
280 class JumpRegMM16<string opstr, RegisterOperand RO> :
281 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
282 [], IIBranch, FrmR> {
283 let hasDelaySlot = 1;
285 let isIndirectBranch = 1;
288 // Base class for JRADDIUSP instruction.
289 class JumpRAddiuStackMM16 :
290 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
291 [], IIBranch, FrmR> {
292 let isTerminator = 1;
295 let isIndirectBranch = 1;
298 // 16-bit Jump and Link (Call) - Short Delay Slot
299 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
300 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
301 [], IIBranch, FrmR> {
303 let hasDelaySlot = 1;
307 // 16-bit Jump Register Compact - No delay slot
308 class JumpRegCMM16<string opstr, RegisterOperand RO> :
309 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
310 [], IIBranch, FrmR> {
311 let isTerminator = 1;
314 let isIndirectBranch = 1;
317 // Break16 and Sdbbp16
318 class BrkSdbbp16MM<string opstr> :
319 MicroMipsInst16<(outs), (ins uimm4:$code_),
320 !strconcat(opstr, "\t$code_"),
321 [], NoItinerary, FrmOther>;
323 // MicroMIPS Jump and Link (Call) - Short Delay Slot
324 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
325 class JumpLinkMM<string opstr, DAGOperand opnd> :
326 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
327 [], IIBranch, FrmJ, opstr> {
328 let DecoderMethod = "DecodeJumpTargetMM";
331 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
332 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
335 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
336 RegisterOperand RO> :
337 InstSE<(outs), (ins RO:$rs, opnd:$offset),
338 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
341 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
342 InstrItinClass Itin = NoItinerary,
343 SDPatternOperator OpNode = null_frag> :
344 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
345 !strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>;
347 /// A list of registers used by load/store multiple instructions.
348 def RegListAsmOperand : AsmOperandClass {
349 let Name = "RegList";
350 let ParserMethod = "parseRegisterList";
353 def reglist : Operand<i32> {
354 let EncoderMethod = "getRegisterListOpValue";
355 let ParserMatchClass = RegListAsmOperand;
356 let PrintMethod = "printRegisterList";
357 let DecoderMethod = "DecodeRegListOperand";
360 def RegList16AsmOperand : AsmOperandClass {
361 let Name = "RegList16";
362 let ParserMethod = "parseRegisterList";
363 let PredicateMethod = "isRegList16";
364 let RenderMethod = "addRegListOperands";
367 def reglist16 : Operand<i32> {
368 let EncoderMethod = "getRegisterListOpValue16";
369 let DecoderMethod = "DecodeRegListOperand16";
370 let PrintMethod = "printRegisterList";
371 let ParserMatchClass = RegList16AsmOperand;
374 class StoreMultMM<string opstr,
375 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
376 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
377 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
378 let DecoderMethod = "DecodeMemMMImm12";
382 class LoadMultMM<string opstr,
383 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
384 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
385 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
386 let DecoderMethod = "DecodeMemMMImm12";
390 class StoreMultMM16<string opstr,
391 InstrItinClass Itin = NoItinerary,
392 ComplexPattern Addr = addr> :
393 MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
394 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
398 class LoadMultMM16<string opstr,
399 InstrItinClass Itin = NoItinerary,
400 ComplexPattern Addr = addr> :
401 MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
402 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
406 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
408 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
410 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>;
411 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
413 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
415 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
417 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>;
418 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
420 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
422 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
423 mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
424 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
425 mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
426 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
427 LOAD_STORE_FM_MM16<0x1a>;
428 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
429 II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
430 def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
431 II_SH, mem_mm_4_lsl1>,
432 LOAD_STORE_FM_MM16<0x2a>;
433 def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
434 mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
435 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
436 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
437 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
438 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
439 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
440 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
441 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
442 def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>, LI_FM_MM16,
444 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
445 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
446 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
447 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
448 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
449 def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>;
450 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>;
452 class WaitMM<string opstr> :
453 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
454 NoItinerary, FrmOther, opstr>;
456 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
457 /// Compact Branch Instructions
458 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
459 COMPACT_BRANCH_FM_MM<0x7>;
460 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
461 COMPACT_BRANCH_FM_MM<0x5>;
463 /// Arithmetic Instructions (ALU Immediate)
464 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
466 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
468 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
470 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
472 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
474 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
476 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
478 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
480 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
483 /// Arithmetic Instructions (3-Operand, R-Type)
484 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
485 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
486 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
487 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
488 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
489 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
490 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
492 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
494 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
496 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
498 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
499 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
501 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
503 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
505 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
508 /// Shift Instructions
509 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
511 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
513 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
515 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
517 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
519 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
521 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
523 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
526 /// Load and Store Instructions - aligned
527 let DecoderMethod = "DecodeMemMMImm16" in {
528 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
529 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
530 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
531 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
532 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
533 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
534 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
535 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
538 def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
540 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
542 /// Load and Store Instructions - unaligned
543 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
545 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
547 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
549 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
552 /// Load and Store Instructions - multiple
553 def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
554 def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>;
555 def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>;
556 def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>;
559 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
560 NoItinerary>, ADD_FM_MM<0, 0x58>;
561 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
562 NoItinerary>, ADD_FM_MM<0, 0x18>;
563 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
564 CMov_F_I_FM_MM<0x25>;
565 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
568 /// Move to/from HI/LO
569 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
571 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
573 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
575 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
578 /// Multiply Add/Sub Instructions
579 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
580 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
581 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
582 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
585 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
587 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
590 /// Sign Ext In Register Instructions.
591 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
592 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
593 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
594 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
596 /// Word Swap Bytes Within Halfwords
597 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,
600 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
602 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
605 /// Jump Instructions
606 let DecoderMethod = "DecodeJumpTargetMM" in {
607 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
609 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
611 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
612 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
614 /// Jump Instructions - Short Delay Slot
615 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
616 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
618 /// Branch Instructions
619 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
621 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
623 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
625 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
627 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
629 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
631 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
633 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
636 /// Branch Instructions - Short Delay Slot
637 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
638 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
639 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
640 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
642 /// Control Instructions
643 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
644 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
645 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
646 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
647 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
648 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
649 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
651 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
654 /// Trap Instructions
655 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
656 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
657 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
658 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
659 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
660 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
662 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
663 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
664 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
665 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
666 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
667 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
669 /// Load-linked, Store-conditional
670 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
671 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
673 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
674 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
675 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
676 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
678 def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
679 def RDHWR_MM : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM;
682 let Predicates = [InMicroMips] in {
684 //===----------------------------------------------------------------------===//
685 // MicroMips arbitrary patterns that map to one or more instructions
686 //===----------------------------------------------------------------------===//
688 def : MipsPat<(i32 immLi16:$imm),
689 (LI16_MM immLi16:$imm)>;
690 def : MipsPat<(i32 immSExt16:$imm),
691 (ADDiu_MM ZERO, immSExt16:$imm)>;
692 def : MipsPat<(i32 immZExt16:$imm),
693 (ORi_MM ZERO, immZExt16:$imm)>;
695 def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
696 (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
697 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
698 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
699 def : MipsPat<(add GPR32:$src, immSExt16:$imm),
700 (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
702 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
703 (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
704 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
705 (ANDi_MM GPR32:$src, immZExt16:$imm)>;
707 def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
708 (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
709 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
710 (SLL_MM GPR32:$src, immZExt5:$imm)>;
712 def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
713 (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
714 def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
715 (SRL_MM GPR32:$src, immZExt5:$imm)>;
717 //===----------------------------------------------------------------------===//
718 // MicroMips instruction aliases
719 //===----------------------------------------------------------------------===//
721 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
722 def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
723 def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;