1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
3 def simm4 : Operand<i32> {
4 let DecoderMethod = "DecodeSimm4";
6 def li_simm7 : Operand<i32> {
7 let DecoderMethod = "DecodeLiSimm7";
10 def simm12 : Operand<i32> {
11 let DecoderMethod = "DecodeSimm12";
14 def uimm5_lsl2 : Operand<OtherVT> {
15 let EncoderMethod = "getUImm5Lsl2Encoding";
16 let DecoderMethod = "DecodeUImm5lsl2";
19 def uimm6_lsl2 : Operand<i32> {
20 let EncoderMethod = "getUImm6Lsl2Encoding";
21 let DecoderMethod = "DecodeUImm6Lsl2";
24 def simm9_addiusp : Operand<i32> {
25 let EncoderMethod = "getSImm9AddiuspValue";
26 let DecoderMethod = "DecodeSimm9SP";
29 def uimm3_shift : Operand<i32> {
30 let EncoderMethod = "getUImm3Mod8Encoding";
33 def simm3_lsa2 : Operand<i32> {
34 let EncoderMethod = "getSImm3Lsa2Value";
35 let DecoderMethod = "DecodeAddiur2Simm7";
38 def uimm4_andi : Operand<i32> {
39 let EncoderMethod = "getUImm4AndValue";
40 let DecoderMethod = "DecodeANDI16Imm";
43 def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
45 Imm < 28 && Imm > 0);}]>;
47 def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
49 def immZExtAndi16 : ImmLeaf<i32,
50 [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
51 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
52 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
54 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
56 def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
58 def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
59 let Name = "MicroMipsMem";
60 let RenderMethod = "addMicroMipsMemOperands";
61 let ParserMethod = "parseMemOperand";
62 let PredicateMethod = "isMemWithGRPMM16Base";
65 class mem_mm_4_generic : Operand<i32> {
66 let PrintMethod = "printMemOperand";
67 let MIOperandInfo = (ops ptr_rc, simm4);
68 let OperandType = "OPERAND_MEMORY";
69 let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
72 def mem_mm_4 : mem_mm_4_generic {
73 let EncoderMethod = "getMemEncodingMMImm4";
76 def mem_mm_4_lsl1 : mem_mm_4_generic {
77 let EncoderMethod = "getMemEncodingMMImm4Lsl1";
80 def mem_mm_4_lsl2 : mem_mm_4_generic {
81 let EncoderMethod = "getMemEncodingMMImm4Lsl2";
84 def MicroMipsMemSPAsmOperand : AsmOperandClass {
85 let Name = "MicroMipsMemSP";
86 let RenderMethod = "addMemOperands";
87 let ParserMethod = "parseMemOperand";
88 let PredicateMethod = "isMemWithUimmWordAlignedOffsetSP<7>";
91 def mem_mm_sp_imm5_lsl2 : Operand<i32> {
92 let PrintMethod = "printMemOperand";
93 let MIOperandInfo = (ops GPR32:$base, simm5:$offset);
94 let OperandType = "OPERAND_MEMORY";
95 let ParserMatchClass = MicroMipsMemSPAsmOperand;
96 let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
99 def mem_mm_12 : Operand<i32> {
100 let PrintMethod = "printMemOperand";
101 let MIOperandInfo = (ops GPR32, simm12);
102 let EncoderMethod = "getMemEncodingMMImm12";
103 let ParserMatchClass = MipsMemAsmOperand;
104 let OperandType = "OPERAND_MEMORY";
107 def MipsMemUimm4AsmOperand : AsmOperandClass {
108 let Name = "MemOffsetUimm4";
109 let SuperClasses = [MipsMemAsmOperand];
110 let RenderMethod = "addMemOperands";
111 let ParserMethod = "parseMemOperand";
112 let PredicateMethod = "isMemWithUimmOffsetSP<6>";
115 def mem_mm_4sp : Operand<i32> {
116 let PrintMethod = "printMemOperand";
117 let MIOperandInfo = (ops GPR32, uimm8);
118 let EncoderMethod = "getMemEncodingMMImm4sp";
119 let ParserMatchClass = MipsMemUimm4AsmOperand;
120 let OperandType = "OPERAND_MEMORY";
123 def jmptarget_mm : Operand<OtherVT> {
124 let EncoderMethod = "getJumpTargetOpValueMM";
127 def calltarget_mm : Operand<iPTR> {
128 let EncoderMethod = "getJumpTargetOpValueMM";
131 def brtarget7_mm : Operand<OtherVT> {
132 let EncoderMethod = "getBranchTarget7OpValueMM";
133 let OperandType = "OPERAND_PCREL";
134 let DecoderMethod = "DecodeBranchTarget7MM";
135 let ParserMatchClass = MipsJumpTargetAsmOperand;
138 def brtarget10_mm : Operand<OtherVT> {
139 let EncoderMethod = "getBranchTargetOpValueMMPC10";
140 let OperandType = "OPERAND_PCREL";
141 let DecoderMethod = "DecodeBranchTarget10MM";
142 let ParserMatchClass = MipsJumpTargetAsmOperand;
145 def brtarget_mm : Operand<OtherVT> {
146 let EncoderMethod = "getBranchTargetOpValueMM";
147 let OperandType = "OPERAND_PCREL";
148 let DecoderMethod = "DecodeBranchTargetMM";
149 let ParserMatchClass = MipsJumpTargetAsmOperand;
152 def simm23_lsl2 : Operand<i32> {
153 let EncoderMethod = "getSimm23Lsl2Encoding";
154 let DecoderMethod = "DecodeSimm23Lsl2";
157 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
158 RegisterOperand RO> :
159 InstSE<(outs), (ins RO:$rs, opnd:$offset),
160 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
162 let isTerminator = 1;
163 let hasDelaySlot = 0;
167 let canFoldAsLoad = 1 in
168 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
170 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
171 !strconcat(opstr, "\t$rt, $addr"),
172 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
174 let DecoderMethod = "DecodeMemMMImm12";
175 string Constraints = "$src = $rt";
178 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
180 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
181 !strconcat(opstr, "\t$rt, $addr"),
182 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
183 let DecoderMethod = "DecodeMemMMImm12";
186 /// A register pair used by load/store pair instructions.
187 def RegPairAsmOperand : AsmOperandClass {
188 let Name = "RegPair";
189 let ParserMethod = "parseRegisterPair";
192 def regpair : Operand<i32> {
193 let EncoderMethod = "getRegisterPairOpValue";
194 let ParserMatchClass = RegPairAsmOperand;
195 let PrintMethod = "printRegisterPair";
196 let DecoderMethod = "DecodeRegPairOperand";
197 let MIOperandInfo = (ops GPR32Opnd, GPR32Opnd);
200 class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary,
201 ComplexPattern Addr = addr> :
202 InstSE<(outs), (ins regpair:$rt, mem_mm_12:$addr),
203 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
204 let DecoderMethod = "DecodeMemMMImm12";
208 class LoadPairMM<string opstr, InstrItinClass Itin = NoItinerary,
209 ComplexPattern Addr = addr> :
210 InstSE<(outs regpair:$rt), (ins mem_mm_12:$addr),
211 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
212 let DecoderMethod = "DecodeMemMMImm12";
216 class LLBaseMM<string opstr, RegisterOperand RO> :
217 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
218 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
219 let DecoderMethod = "DecodeMemMMImm12";
223 class SCBaseMM<string opstr, RegisterOperand RO> :
224 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
225 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
226 let DecoderMethod = "DecodeMemMMImm12";
228 let Constraints = "$rt = $dst";
231 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
232 InstrItinClass Itin = NoItinerary> :
233 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
234 !strconcat(opstr, "\t$rt, $addr"),
235 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
236 let DecoderMethod = "DecodeMemMMImm12";
237 let canFoldAsLoad = 1;
241 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
242 InstrItinClass Itin = NoItinerary,
243 SDPatternOperator OpNode = null_frag> :
244 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
245 !strconcat(opstr, "\t$rd, $rs, $rt"),
246 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
247 let isCommutable = isComm;
250 class AndImmMM16<string opstr, RegisterOperand RO,
251 InstrItinClass Itin = NoItinerary> :
252 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
253 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
255 class LogicRMM16<string opstr, RegisterOperand RO,
256 InstrItinClass Itin = NoItinerary,
257 SDPatternOperator OpNode = null_frag> :
258 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
259 !strconcat(opstr, "\t$rt, $rs"),
260 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
261 let isCommutable = 1;
262 let Constraints = "$rt = $dst";
265 class NotMM16<string opstr, RegisterOperand RO> :
266 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
267 !strconcat(opstr, "\t$rt, $rs"),
268 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
270 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
271 InstrItinClass Itin = NoItinerary> :
272 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
273 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
275 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
276 InstrItinClass Itin, Operand MemOpnd> :
277 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
278 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
279 let DecoderMethod = "DecodeMemMMImm4";
280 let canFoldAsLoad = 1;
284 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
285 SDPatternOperator OpNode, InstrItinClass Itin,
287 MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
288 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
289 let DecoderMethod = "DecodeMemMMImm4";
293 class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
295 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
296 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
297 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
298 let canFoldAsLoad = 1;
302 class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
304 MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
305 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
306 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
310 class AddImmUR2<string opstr, RegisterOperand RO> :
311 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
312 !strconcat(opstr, "\t$rd, $rs, $imm"),
313 [], NoItinerary, FrmR> {
314 let isCommutable = 1;
317 class AddImmUS5<string opstr, RegisterOperand RO> :
318 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
319 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
320 let Constraints = "$rd = $dst";
323 class AddImmUR1SP<string opstr, RegisterOperand RO> :
324 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
325 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
327 class AddImmUSP<string opstr> :
328 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
329 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
331 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
332 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
333 [], II_MFHI_MFLO, FrmR> {
335 let hasSideEffects = 0;
338 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
339 InstrItinClass Itin = NoItinerary> :
340 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
341 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
342 let isCommutable = isComm;
343 let isReMaterializable = 1;
346 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
347 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
348 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
349 let isReMaterializable = 1;
352 // 16-bit Jump and Link (Call)
353 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
354 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
355 [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
357 let hasDelaySlot = 1;
362 class JumpRegMM16<string opstr, RegisterOperand RO> :
363 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
364 [], IIBranch, FrmR> {
365 let hasDelaySlot = 1;
367 let isIndirectBranch = 1;
370 // Base class for JRADDIUSP instruction.
371 class JumpRAddiuStackMM16 :
372 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
373 [], IIBranch, FrmR> {
374 let isTerminator = 1;
377 let isIndirectBranch = 1;
380 // 16-bit Jump and Link (Call) - Short Delay Slot
381 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
382 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
383 [], IIBranch, FrmR> {
385 let hasDelaySlot = 1;
389 // 16-bit Jump Register Compact - No delay slot
390 class JumpRegCMM16<string opstr, RegisterOperand RO> :
391 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
392 [], IIBranch, FrmR> {
393 let isTerminator = 1;
396 let isIndirectBranch = 1;
399 // Break16 and Sdbbp16
400 class BrkSdbbp16MM<string opstr> :
401 MicroMipsInst16<(outs), (ins uimm4:$code_),
402 !strconcat(opstr, "\t$code_"),
403 [], NoItinerary, FrmOther>;
405 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
406 MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
407 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
409 let isTerminator = 1;
410 let hasDelaySlot = 1;
414 // MicroMIPS Jump and Link (Call) - Short Delay Slot
415 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
416 class JumpLinkMM<string opstr, DAGOperand opnd> :
417 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
418 [], IIBranch, FrmJ, opstr> {
419 let DecoderMethod = "DecodeJumpTargetMM";
422 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
423 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
426 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
427 RegisterOperand RO> :
428 InstSE<(outs), (ins RO:$rs, opnd:$offset),
429 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
432 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
433 InstrItinClass Itin = NoItinerary,
434 SDPatternOperator OpNode = null_frag> :
435 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
436 !strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>;
438 class AddImmUPC<string opstr, RegisterOperand RO> :
439 InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
440 !strconcat(opstr, "\t$rs, $imm"), [], NoItinerary, FrmR>;
442 /// A list of registers used by load/store multiple instructions.
443 def RegListAsmOperand : AsmOperandClass {
444 let Name = "RegList";
445 let ParserMethod = "parseRegisterList";
448 def reglist : Operand<i32> {
449 let EncoderMethod = "getRegisterListOpValue";
450 let ParserMatchClass = RegListAsmOperand;
451 let PrintMethod = "printRegisterList";
452 let DecoderMethod = "DecodeRegListOperand";
455 def RegList16AsmOperand : AsmOperandClass {
456 let Name = "RegList16";
457 let ParserMethod = "parseRegisterList";
458 let PredicateMethod = "isRegList16";
459 let RenderMethod = "addRegListOperands";
462 def reglist16 : Operand<i32> {
463 let EncoderMethod = "getRegisterListOpValue16";
464 let DecoderMethod = "DecodeRegListOperand16";
465 let PrintMethod = "printRegisterList";
466 let ParserMatchClass = RegList16AsmOperand;
469 class StoreMultMM<string opstr,
470 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
471 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
472 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
473 let DecoderMethod = "DecodeMemMMImm12";
477 class LoadMultMM<string opstr,
478 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
479 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
480 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
481 let DecoderMethod = "DecodeMemMMImm12";
485 class StoreMultMM16<string opstr,
486 InstrItinClass Itin = NoItinerary,
487 ComplexPattern Addr = addr> :
488 MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
489 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
493 class LoadMultMM16<string opstr,
494 InstrItinClass Itin = NoItinerary,
495 ComplexPattern Addr = addr> :
496 MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
497 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
501 class UncondBranchMM16<string opstr> :
502 MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
503 !strconcat(opstr, "\t$offset"),
504 [], IIBranch, FrmI> {
506 let isTerminator = 1;
508 let hasDelaySlot = 1;
509 let Predicates = [RelocPIC, InMicroMips];
513 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
515 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
517 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>;
518 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
520 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
522 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
524 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>;
525 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
527 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
529 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
530 mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
531 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
532 mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
533 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
534 LOAD_STORE_FM_MM16<0x1a>;
535 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
536 II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
537 def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
538 II_SH, mem_mm_4_lsl1>,
539 LOAD_STORE_FM_MM16<0x2a>;
540 def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
541 mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
542 def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
543 LOAD_STORE_SP_FM_MM16<0x12>;
544 def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
545 LOAD_STORE_SP_FM_MM16<0x32>;
546 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
547 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
548 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
549 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
550 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
551 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
552 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
553 def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>, LI_FM_MM16,
555 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
556 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
557 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
558 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
559 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
560 def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
561 BEQNEZ_FM_MM16<0x23>;
562 def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
563 BEQNEZ_FM_MM16<0x2b>;
564 def B16_MM : UncondBranchMM16<"b16">, B16_FM;
565 def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>;
566 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>;
568 class WaitMM<string opstr> :
569 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
570 NoItinerary, FrmOther, opstr>;
572 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
573 /// Compact Branch Instructions
574 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
575 COMPACT_BRANCH_FM_MM<0x7>;
576 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
577 COMPACT_BRANCH_FM_MM<0x5>;
579 /// Arithmetic Instructions (ALU Immediate)
580 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
582 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
584 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
586 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
588 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
590 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
592 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
594 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
596 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
599 /// Arithmetic Instructions (3-Operand, R-Type)
600 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
601 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
602 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
603 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
604 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
605 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
606 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
608 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
610 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
612 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
614 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
615 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
617 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
619 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
621 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
624 /// Arithmetic Instructions with PC and Immediate
625 def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
627 /// Shift Instructions
628 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
630 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
632 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
634 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
636 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
638 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
640 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
642 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
645 /// Load and Store Instructions - aligned
646 let DecoderMethod = "DecodeMemMMImm16" in {
647 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
648 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
649 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
650 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
651 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
652 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
653 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
654 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
657 def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
659 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
661 /// Load and Store Instructions - unaligned
662 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
664 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
666 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
668 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
671 /// Load and Store Instructions - multiple
672 def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
673 def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>;
674 def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>;
675 def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>;
677 /// Load and Store Pair Instructions
678 def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>;
679 def LWP_MM : LoadPairMM<"lwp">, LWM_FM_MM<0x1>;
682 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
683 NoItinerary>, ADD_FM_MM<0, 0x58>;
684 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
685 NoItinerary>, ADD_FM_MM<0, 0x18>;
686 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
687 CMov_F_I_FM_MM<0x25>;
688 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
691 /// Move to/from HI/LO
692 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
694 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
696 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
698 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
701 /// Multiply Add/Sub Instructions
702 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
703 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
704 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
705 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
708 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
710 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
713 /// Sign Ext In Register Instructions.
714 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
715 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
716 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
717 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
719 /// Word Swap Bytes Within Halfwords
720 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,
723 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
725 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
728 /// Jump Instructions
729 let DecoderMethod = "DecodeJumpTargetMM" in {
730 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
732 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
734 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
735 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
737 /// Jump Instructions - Short Delay Slot
738 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
739 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
741 /// Branch Instructions
742 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
744 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
746 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
748 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
750 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
752 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
754 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
756 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
759 /// Branch Instructions - Short Delay Slot
760 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
761 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
762 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
763 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
765 /// Control Instructions
766 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
767 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
768 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
769 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
770 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
771 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
772 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
774 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
777 /// Trap Instructions
778 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
779 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
780 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
781 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
782 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
783 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
785 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
786 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
787 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
788 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
789 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
790 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
792 /// Load-linked, Store-conditional
793 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
794 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
796 let DecoderMethod = "DecodeCacheOpMM" in {
797 def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12>,
798 CACHE_PREF_FM_MM<0x08, 0x6>;
799 def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12>,
800 CACHE_PREF_FM_MM<0x18, 0x2>;
802 def SSNOP_MM : MMRel, Barrier<"ssnop">, BARRIER_FM_MM<0x1>;
803 def EHB_MM : MMRel, Barrier<"ehb">, BARRIER_FM_MM<0x3>;
804 def PAUSE_MM : MMRel, Barrier<"pause">, BARRIER_FM_MM<0x5>;
806 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
807 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
808 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
809 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
811 def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
812 def RDHWR_MM : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM;
815 let Predicates = [InMicroMips] in {
817 //===----------------------------------------------------------------------===//
818 // MicroMips arbitrary patterns that map to one or more instructions
819 //===----------------------------------------------------------------------===//
821 def : MipsPat<(i32 immLi16:$imm),
822 (LI16_MM immLi16:$imm)>;
823 def : MipsPat<(i32 immSExt16:$imm),
824 (ADDiu_MM ZERO, immSExt16:$imm)>;
825 def : MipsPat<(i32 immZExt16:$imm),
826 (ORi_MM ZERO, immZExt16:$imm)>;
828 def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
829 (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
830 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
831 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
832 def : MipsPat<(add GPR32:$src, immSExt16:$imm),
833 (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
835 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
836 (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
837 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
838 (ANDi_MM GPR32:$src, immZExt16:$imm)>;
840 def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
841 (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
842 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
843 (SLL_MM GPR32:$src, immZExt5:$imm)>;
845 def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
846 (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
847 def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
848 (SRL_MM GPR32:$src, immZExt5:$imm)>;
850 //===----------------------------------------------------------------------===//
851 // MicroMips instruction aliases
852 //===----------------------------------------------------------------------===//
854 class UncondBranchMMPseudo<string opstr> :
855 MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
856 !strconcat(opstr, "\t$offset")>;
858 def B_MM_Pseudo : UncondBranchMMPseudo<"b">;
860 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
861 def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
862 def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;