1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
3 def simm12 : Operand<i32> {
4 let DecoderMethod = "DecodeSimm12";
7 def mem_mm_12 : Operand<i32> {
8 let PrintMethod = "printMemOperand";
9 let MIOperandInfo = (ops GPR32, simm12);
10 let EncoderMethod = "getMemEncodingMMImm12";
11 let ParserMatchClass = MipsMemAsmOperand;
12 let OperandType = "OPERAND_MEMORY";
15 def jmptarget_mm : Operand<OtherVT> {
16 let EncoderMethod = "getJumpTargetOpValueMM";
19 def calltarget_mm : Operand<iPTR> {
20 let EncoderMethod = "getJumpTargetOpValueMM";
23 def brtarget_mm : Operand<OtherVT> {
24 let EncoderMethod = "getBranchTargetOpValueMM";
25 let OperandType = "OPERAND_PCREL";
26 let DecoderMethod = "DecodeBranchTargetMM";
29 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
31 InstSE<(outs), (ins RO:$rs, opnd:$offset),
32 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
39 let canFoldAsLoad = 1 in
40 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
42 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
43 !strconcat(opstr, "\t$rt, $addr"),
44 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
46 let DecoderMethod = "DecodeMemMMImm12";
47 string Constraints = "$src = $rt";
50 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
52 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
53 !strconcat(opstr, "\t$rt, $addr"),
54 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
55 let DecoderMethod = "DecodeMemMMImm12";
58 class LLBaseMM<string opstr, RegisterOperand RO> :
59 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
60 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
61 let DecoderMethod = "DecodeMemMMImm12";
65 class SCBaseMM<string opstr, RegisterOperand RO> :
66 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
67 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
68 let DecoderMethod = "DecodeMemMMImm12";
70 let Constraints = "$rt = $dst";
73 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
74 InstrItinClass Itin = NoItinerary> :
75 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
76 !strconcat(opstr, "\t$rt, $addr"),
77 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
78 let DecoderMethod = "DecodeMemMMImm12";
79 let canFoldAsLoad = 1;
83 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
84 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
85 [], II_MFHI_MFLO, FrmR> {
87 let hasSideEffects = 0;
90 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
91 InstrItinClass Itin = NoItinerary> :
92 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
93 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
94 let isCommutable = isComm;
95 let isReMaterializable = 1;
98 // 16-bit Jump and Link (Call)
99 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
100 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
101 [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
103 let hasDelaySlot = 1;
107 // MicroMIPS Jump and Link (Call) - Short Delay Slot
108 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
109 class JumpLinkMM<string opstr, DAGOperand opnd> :
110 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
111 [], IIBranch, FrmJ, opstr> {
112 let DecoderMethod = "DecodeJumpTargetMM";
115 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
116 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
120 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
121 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
122 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
123 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
125 class WaitMM<string opstr> :
126 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
127 NoItinerary, FrmOther, opstr>;
129 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
130 /// Compact Branch Instructions
131 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
132 COMPACT_BRANCH_FM_MM<0x7>;
133 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
134 COMPACT_BRANCH_FM_MM<0x5>;
136 /// Arithmetic Instructions (ALU Immediate)
137 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
139 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
141 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
143 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
145 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
147 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
149 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
151 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
153 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
156 /// Arithmetic Instructions (3-Operand, R-Type)
157 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
158 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
159 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
160 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
161 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
162 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
163 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
165 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
167 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
169 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
171 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
172 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
174 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
176 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
178 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
181 /// Shift Instructions
182 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
184 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
186 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
188 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
190 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
192 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
194 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
196 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
199 /// Load and Store Instructions - aligned
200 let DecoderMethod = "DecodeMemMMImm16" in {
201 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
202 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
203 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
204 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
205 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
206 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
207 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
208 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
211 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
213 /// Load and Store Instructions - unaligned
214 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
216 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
218 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
220 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
224 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
225 NoItinerary>, ADD_FM_MM<0, 0x58>;
226 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
227 NoItinerary>, ADD_FM_MM<0, 0x18>;
228 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
229 CMov_F_I_FM_MM<0x25>;
230 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
233 /// Move to/from HI/LO
234 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
236 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
238 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
240 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
243 /// Multiply Add/Sub Instructions
244 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
245 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
246 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
247 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
250 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
252 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
255 /// Sign Ext In Register Instructions.
256 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
257 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
258 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
259 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
261 /// Word Swap Bytes Within Halfwords
262 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,
265 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
267 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
270 /// Jump Instructions
271 let DecoderMethod = "DecodeJumpTargetMM" in {
272 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
274 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
276 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
277 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
279 /// Jump Instructions - Short Delay Slot
280 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
281 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
283 /// Branch Instructions
284 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
286 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
288 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
290 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
292 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
294 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
296 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
298 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
301 /// Control Instructions
302 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
303 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
304 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
305 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
306 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
307 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
308 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
310 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
313 /// Trap Instructions
314 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
315 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
316 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
317 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
318 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
319 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
321 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
322 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
323 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
324 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
325 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
326 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
328 /// Load-linked, Store-conditional
329 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
330 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
332 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
333 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
334 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
335 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
338 //===----------------------------------------------------------------------===//
339 // MicroMips instruction aliases
340 //===----------------------------------------------------------------------===//
342 let Predicates = [InMicroMips] in {
343 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;