1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
3 def simm12 : Operand<i32> {
4 let DecoderMethod = "DecodeSimm12";
7 def mem_mm_12 : Operand<i32> {
8 let PrintMethod = "printMemOperand";
9 let MIOperandInfo = (ops GPR32, simm12);
10 let EncoderMethod = "getMemEncodingMMImm12";
11 let ParserMatchClass = MipsMemAsmOperand;
12 let OperandType = "OPERAND_MEMORY";
15 let canFoldAsLoad = 1 in
16 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
18 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
19 !strconcat(opstr, "\t$rt, $addr"),
20 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
22 string Constraints = "$src = $rt";
25 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
27 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
28 !strconcat(opstr, "\t$rt, $addr"),
29 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI>;
31 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
32 /// Arithmetic Instructions (ALU Immediate)
33 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
35 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
37 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
39 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
41 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
43 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
45 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
47 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
49 /// Arithmetic Instructions (3-Operand, R-Type)
50 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
51 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
52 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
53 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
54 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
55 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
56 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
58 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IIAlu, and>,
60 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IIAlu, or>,
62 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IIAlu, xor>,
64 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
65 def MULT_MM : MMRel, Mult<"mult", IIImul, GPR32Opnd, [HI0, LO0]>,
67 def MULTu_MM : MMRel, Mult<"multu", IIImul, GPR32Opnd, [HI0, LO0]>,
70 /// Shift Instructions
71 def SLL_MM : MMRel, shift_rotate_imm<"sll", shamt, GPR32Opnd>,
73 def SRL_MM : MMRel, shift_rotate_imm<"srl", shamt, GPR32Opnd>,
75 def SRA_MM : MMRel, shift_rotate_imm<"sra", shamt, GPR32Opnd>,
77 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd>,
79 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd>,
81 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd>,
83 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", shamt, GPR32Opnd>,
85 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd>,
88 /// Load and Store Instructions - aligned
89 def LB_MM : Load<"lb", GPR32Opnd, sextloadi8>, MMRel, LW_FM_MM<0x7>;
90 def LBu_MM : Load<"lbu", GPR32Opnd, zextloadi8>, MMRel, LW_FM_MM<0x5>;
91 def LH_MM : Load<"lh", GPR32Opnd, sextloadi16>, MMRel, LW_FM_MM<0xf>;
92 def LHu_MM : Load<"lhu", GPR32Opnd, zextloadi16>, MMRel, LW_FM_MM<0xd>;
93 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
94 def SB_MM : Store<"sb", GPR32Opnd, truncstorei8>, MMRel, LW_FM_MM<0x6>;
95 def SH_MM : Store<"sh", GPR32Opnd, truncstorei16>, MMRel, LW_FM_MM<0xe>;
96 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
98 /// Load and Store Instructions - unaligned
99 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
101 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
103 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
105 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,