1 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
3 def simm4 : Operand<i32>;
4 def simm7 : Operand<i32>;
6 def simm12 : Operand<i32> {
7 let DecoderMethod = "DecodeSimm12";
10 def uimm5_lsl2 : Operand<OtherVT> {
11 let EncoderMethod = "getUImm5Lsl2Encoding";
14 def uimm6_lsl2 : Operand<i32> {
15 let EncoderMethod = "getUImm6Lsl2Encoding";
18 def simm9_addiusp : Operand<i32> {
19 let EncoderMethod = "getSImm9AddiuspValue";
22 def uimm3_shift : Operand<i32> {
23 let EncoderMethod = "getUImm3Mod8Encoding";
26 def simm3_lsa2 : Operand<i32> {
27 let EncoderMethod = "getSImm3Lsa2Value";
30 def uimm4_andi : Operand<i32> {
31 let EncoderMethod = "getUImm4AndValue";
34 def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
36 Imm < 28 && Imm > 0);}]>;
38 def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
40 def immZExtAndi16 : ImmLeaf<i32,
41 [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
42 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
43 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
45 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
47 def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
49 def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
50 let Name = "MicroMipsMem";
51 let RenderMethod = "addMicroMipsMemOperands";
52 let ParserMethod = "parseMemOperand";
53 let PredicateMethod = "isMemWithGRPMM16Base";
56 class mem_mm_4_generic : Operand<i32> {
57 let PrintMethod = "printMemOperand";
58 let MIOperandInfo = (ops ptr_rc, simm4);
59 let OperandType = "OPERAND_MEMORY";
60 let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
63 def mem_mm_4 : mem_mm_4_generic {
64 let EncoderMethod = "getMemEncodingMMImm4";
67 def mem_mm_4_lsl1 : mem_mm_4_generic {
68 let EncoderMethod = "getMemEncodingMMImm4Lsl1";
71 def mem_mm_4_lsl2 : mem_mm_4_generic {
72 let EncoderMethod = "getMemEncodingMMImm4Lsl2";
75 def mem_mm_12 : Operand<i32> {
76 let PrintMethod = "printMemOperand";
77 let MIOperandInfo = (ops GPR32, simm12);
78 let EncoderMethod = "getMemEncodingMMImm12";
79 let ParserMatchClass = MipsMemAsmOperand;
80 let OperandType = "OPERAND_MEMORY";
83 def jmptarget_mm : Operand<OtherVT> {
84 let EncoderMethod = "getJumpTargetOpValueMM";
87 def calltarget_mm : Operand<iPTR> {
88 let EncoderMethod = "getJumpTargetOpValueMM";
91 def brtarget_mm : Operand<OtherVT> {
92 let EncoderMethod = "getBranchTargetOpValueMM";
93 let OperandType = "OPERAND_PCREL";
94 let DecoderMethod = "DecodeBranchTargetMM";
97 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
99 InstSE<(outs), (ins RO:$rs, opnd:$offset),
100 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> {
102 let isTerminator = 1;
103 let hasDelaySlot = 0;
107 let canFoldAsLoad = 1 in
108 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
110 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
111 !strconcat(opstr, "\t$rt, $addr"),
112 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
114 let DecoderMethod = "DecodeMemMMImm12";
115 string Constraints = "$src = $rt";
118 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
120 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
121 !strconcat(opstr, "\t$rt, $addr"),
122 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
123 let DecoderMethod = "DecodeMemMMImm12";
126 class LLBaseMM<string opstr, RegisterOperand RO> :
127 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
128 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
129 let DecoderMethod = "DecodeMemMMImm12";
133 class SCBaseMM<string opstr, RegisterOperand RO> :
134 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
135 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
136 let DecoderMethod = "DecodeMemMMImm12";
138 let Constraints = "$rt = $dst";
141 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
142 InstrItinClass Itin = NoItinerary> :
143 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
144 !strconcat(opstr, "\t$rt, $addr"),
145 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
146 let DecoderMethod = "DecodeMemMMImm12";
147 let canFoldAsLoad = 1;
151 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
152 InstrItinClass Itin = NoItinerary,
153 SDPatternOperator OpNode = null_frag> :
154 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
155 !strconcat(opstr, "\t$rd, $rs, $rt"),
156 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
157 let isCommutable = isComm;
160 class AndImmMM16<string opstr, RegisterOperand RO,
161 InstrItinClass Itin = NoItinerary> :
162 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
163 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
165 class LogicRMM16<string opstr, RegisterOperand RO,
166 InstrItinClass Itin = NoItinerary,
167 SDPatternOperator OpNode = null_frag> :
168 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
169 !strconcat(opstr, "\t$rt, $rs"),
170 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
171 let isCommutable = 1;
172 let Constraints = "$rt = $dst";
175 class NotMM16<string opstr, RegisterOperand RO> :
176 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
177 !strconcat(opstr, "\t$rt, $rs"),
178 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
180 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
181 InstrItinClass Itin = NoItinerary> :
182 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
183 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
185 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
186 InstrItinClass Itin, Operand MemOpnd> :
187 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
188 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
189 let canFoldAsLoad = 1;
193 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
194 SDPatternOperator OpNode, InstrItinClass Itin,
196 MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
197 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
201 class AddImmUR2<string opstr, RegisterOperand RO> :
202 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
203 !strconcat(opstr, "\t$rd, $rs, $imm"),
204 [], NoItinerary, FrmR> {
205 let isCommutable = 1;
208 class AddImmUS5<string opstr, RegisterOperand RO> :
209 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
210 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
211 let Constraints = "$rd = $dst";
214 class AddImmUR1SP<string opstr, RegisterOperand RO> :
215 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
216 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>;
218 class AddImmUSP<string opstr> :
219 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
220 !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
222 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
223 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
224 [], II_MFHI_MFLO, FrmR> {
226 let hasSideEffects = 0;
229 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
230 InstrItinClass Itin = NoItinerary> :
231 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
232 !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
233 let isCommutable = isComm;
234 let isReMaterializable = 1;
237 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO,
238 SDPatternOperator imm_type = null_frag> :
239 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
240 !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> {
241 let isReMaterializable = 1;
244 // 16-bit Jump and Link (Call)
245 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
246 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
247 [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
249 let hasDelaySlot = 1;
254 class JumpRegMM16<string opstr, RegisterOperand RO> :
255 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
256 [], IIBranch, FrmR> {
257 let hasDelaySlot = 1;
259 let isIndirectBranch = 1;
262 // Base class for JRADDIUSP instruction.
263 class JumpRAddiuStackMM16 :
264 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
265 [], IIBranch, FrmR> {
266 let isTerminator = 1;
268 let hasDelaySlot = 1;
270 let isIndirectBranch = 1;
273 // 16-bit Jump and Link (Call) - Short Delay Slot
274 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
275 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
276 [], IIBranch, FrmR> {
278 let hasDelaySlot = 1;
282 // 16-bit Jump Register Compact - No delay slot
283 class JumpRegCMM16<string opstr, RegisterOperand RO> :
284 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
285 [], IIBranch, FrmR> {
286 let isTerminator = 1;
289 let isIndirectBranch = 1;
292 // MicroMIPS Jump and Link (Call) - Short Delay Slot
293 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
294 class JumpLinkMM<string opstr, DAGOperand opnd> :
295 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
296 [], IIBranch, FrmJ, opstr> {
297 let DecoderMethod = "DecodeJumpTargetMM";
300 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
301 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
304 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
305 RegisterOperand RO> :
306 InstSE<(outs), (ins RO:$rs, opnd:$offset),
307 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
310 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
311 InstrItinClass Itin = NoItinerary,
312 SDPatternOperator OpNode = null_frag> :
313 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
314 !strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>;
316 /// A list of registers used by load/store multiple instructions.
317 def RegListAsmOperand : AsmOperandClass {
318 let Name = "RegList";
319 let ParserMethod = "parseRegisterList";
322 def reglist : Operand<i32> {
323 let EncoderMethod = "getRegisterListOpValue";
324 let ParserMatchClass = RegListAsmOperand;
325 let PrintMethod = "printRegisterList";
326 let DecoderMethod = "DecodeRegListOperand";
329 class StoreMultMM<string opstr,
330 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
331 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
332 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
333 let DecoderMethod = "DecodeMemMMImm12";
337 class LoadMultMM<string opstr,
338 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
339 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
340 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
341 let DecoderMethod = "DecodeMemMMImm12";
345 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
347 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
349 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>;
350 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
352 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
354 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
356 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>;
357 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
359 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
361 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
362 mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
363 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
364 mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
365 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
366 LOAD_STORE_FM_MM16<0x1a>;
367 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
368 II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
369 def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
370 II_SH, mem_mm_4_lsl1>,
371 LOAD_STORE_FM_MM16<0x2a>;
372 def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
373 mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
374 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
375 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
376 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
377 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
378 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
379 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
380 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
381 def LI16_MM : LoadImmMM16<"li16", simm7, GPRMM16Opnd, immLi16>,
382 LI_FM_MM16, IsAsCheapAsAMove;
383 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
384 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
385 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
386 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
387 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
389 class WaitMM<string opstr> :
390 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
391 NoItinerary, FrmOther, opstr>;
393 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
394 /// Compact Branch Instructions
395 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
396 COMPACT_BRANCH_FM_MM<0x7>;
397 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
398 COMPACT_BRANCH_FM_MM<0x5>;
400 /// Arithmetic Instructions (ALU Immediate)
401 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
403 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
405 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
407 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
409 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
411 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
413 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
415 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
417 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
420 /// Arithmetic Instructions (3-Operand, R-Type)
421 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
422 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
423 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
424 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
425 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
426 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
427 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
429 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
431 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
433 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
435 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
436 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
438 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
440 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
442 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
445 /// Shift Instructions
446 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
448 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
450 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
452 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
454 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
456 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
458 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
460 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
463 /// Load and Store Instructions - aligned
464 let DecoderMethod = "DecodeMemMMImm16" in {
465 def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
466 def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
467 def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
468 def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
469 def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
470 def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
471 def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
472 def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
475 def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
477 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
479 /// Load and Store Instructions - unaligned
480 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
482 def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
484 def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
486 def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
489 /// Load and Store Instructions - multiple
490 def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
491 def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>;
494 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
495 NoItinerary>, ADD_FM_MM<0, 0x58>;
496 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
497 NoItinerary>, ADD_FM_MM<0, 0x18>;
498 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
499 CMov_F_I_FM_MM<0x25>;
500 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
503 /// Move to/from HI/LO
504 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
506 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
508 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
510 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
513 /// Multiply Add/Sub Instructions
514 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
515 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
516 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
517 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
520 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
522 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
525 /// Sign Ext In Register Instructions.
526 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
527 SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
528 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
529 SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
531 /// Word Swap Bytes Within Halfwords
532 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>,
535 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
537 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
540 /// Jump Instructions
541 let DecoderMethod = "DecodeJumpTargetMM" in {
542 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
544 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
546 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
547 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
549 /// Jump Instructions - Short Delay Slot
550 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
551 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
553 /// Branch Instructions
554 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
556 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
558 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
560 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
562 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
564 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
566 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
568 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
571 /// Branch Instructions - Short Delay Slot
572 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
573 GPR32Opnd>, BGEZAL_FM_MM<0x13>;
574 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
575 GPR32Opnd>, BGEZAL_FM_MM<0x11>;
577 /// Control Instructions
578 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
579 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
580 def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
581 def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
582 def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
583 def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
584 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
586 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
589 /// Trap Instructions
590 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
591 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
592 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
593 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
594 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
595 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
597 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
598 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
599 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
600 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
601 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
602 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
604 /// Load-linked, Store-conditional
605 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
606 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
608 def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
609 def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
610 def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
611 def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
613 def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
614 def RDHWR_MM : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM;
617 let Predicates = [InMicroMips] in {
619 //===----------------------------------------------------------------------===//
620 // MicroMips arbitrary patterns that map to one or more instructions
621 //===----------------------------------------------------------------------===//
623 def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
624 (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
625 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
626 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
627 def : MipsPat<(add GPR32:$src, immSExt16:$imm),
628 (ADDiu_MM GPR32:$src, immSExt16:$imm)>;
630 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
631 (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
632 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
633 (ANDi_MM GPR32:$src, immZExt16:$imm)>;
635 def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
636 (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
637 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
638 (SLL_MM GPR32:$src, immZExt5:$imm)>;
640 def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
641 (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
642 def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
643 (SRL_MM GPR32:$src, immZExt5:$imm)>;
645 //===----------------------------------------------------------------------===//
646 // MicroMips instruction aliases
647 //===----------------------------------------------------------------------===//
649 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;