1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This is the top level entry point for the Mips target.
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 // Target-independent interfaces
14 //===----------------------------------------------------------------------===//
16 include "llvm/Target/Target.td"
18 // The overall idea of the PredicateControl class is to chop the Predicates list
19 // into subsets that are usually overridden independently. This allows
20 // subclasses to partially override the predicates of their superclasses without
21 // having to re-add all the existing predicates.
22 class PredicateControl {
23 // Predicates for the encoding scheme in use such as HasStdEnc
24 list<Predicate> EncodingPredicates = [];
25 // Predicates for the GPR size such as IsGP64bit
26 list<Predicate> GPRPredicates = [];
27 // Predicates for the FGR size and layout such as IsFP64bit
28 list<Predicate> FGRPredicates = [];
29 // Predicates for the instruction group membership such as ISA's and ASE's
30 list<Predicate> InsnPredicates = [];
31 // Predicates for anything else
32 list<Predicate> AdditionalPredicates = [];
33 list<Predicate> Predicates = !listconcat(EncodingPredicates,
37 AdditionalPredicates);
40 // Like Requires<> but for the AdditionalPredicates list
41 class AdditionalRequires<list<Predicate> preds> {
42 list<Predicate> AdditionalPredicates = preds;
45 //===----------------------------------------------------------------------===//
46 // Register File, Calling Conv, Instruction Descriptions
47 //===----------------------------------------------------------------------===//
49 include "MipsRegisterInfo.td"
50 include "MipsSchedule.td"
51 include "MipsInstrInfo.td"
52 include "MipsCallingConv.td"
54 def MipsInstrInfo : InstrInfo;
56 //===----------------------------------------------------------------------===//
57 // Mips Subtarget features //
58 //===----------------------------------------------------------------------===//
60 def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true",
61 "Disable SVR4-style position-independent code.">;
62 def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
63 "General Purpose Registers are 64-bit wide.">;
64 def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
65 "Support 64-bit FP registers.">;
66 def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true",
68 def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
69 "IEEE 754-2008 NaN encoding.">;
70 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
71 "true", "Only supports single precision float">;
72 def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
73 "Disable odd numbered single-precision "
75 def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
76 "true", "Enable vector FPU instructions.">;
77 def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
78 "Mips I ISA Support [highly experimental]">;
79 def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
80 "Mips II ISA Support [highly experimental]",
82 def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
83 "Subset of MIPS-III that is also in MIPS32 "
84 "[highly experimental]">;
85 def FeatureMips3_32r2 : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
86 "Subset of MIPS-III that is also in MIPS32r2 "
87 "[highly experimental]">;
88 def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
89 "MIPS III ISA Support [highly experimental]",
90 [FeatureMips2, FeatureMips3_32,
91 FeatureMips3_32r2, FeatureGP64Bit,
93 def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
94 "Subset of MIPS-IV that is also in MIPS32 "
95 "[highly experimental]">;
96 def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
97 "Subset of MIPS-IV that is also in MIPS32r2 "
98 "[highly experimental]">;
99 def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
100 "Mips4", "MIPS IV ISA Support",
101 [FeatureMips3, FeatureMips4_32,
103 def FeatureMips5_32r2 : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
104 "Subset of MIPS-V that is also in MIPS32r2 "
105 "[highly experimental]">;
106 def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
107 "MIPS V ISA Support [highly experimental]",
108 [FeatureMips4, FeatureMips5_32r2]>;
109 def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
110 "Mips32 ISA Support",
111 [FeatureMips2, FeatureMips3_32,
113 def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
114 "Mips32r2", "Mips32r2 ISA Support",
115 [FeatureMips3_32r2, FeatureMips4_32r2,
116 FeatureMips5_32r2, FeatureMips32]>;
117 def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
119 "Mips32r6 ISA Support [experimental]",
120 [FeatureMips32r2, FeatureFP64Bit,
122 def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
123 "Mips64", "Mips64 ISA Support",
124 [FeatureMips5, FeatureMips32]>;
125 def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
126 "Mips64r2", "Mips64r2 ISA Support",
127 [FeatureMips64, FeatureMips32r2]>;
128 def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion",
130 "Mips64r6 ISA Support [experimental]",
131 [FeatureMips32r6, FeatureMips64r2,
134 def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
137 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
138 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
139 "Mips DSP-R2 ASE", [FeatureDSP]>;
141 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
143 def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
146 def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
147 "true", "Octeon cnMIPS Support",
150 //===----------------------------------------------------------------------===//
151 // Mips processors supported.
152 //===----------------------------------------------------------------------===//
154 class Proc<string Name, list<SubtargetFeature> Features>
155 : Processor<Name, MipsGenericItineraries, Features>;
157 def : Proc<"mips1", [FeatureMips1]>;
158 def : Proc<"mips2", [FeatureMips2]>;
159 def : Proc<"mips32", [FeatureMips32]>;
160 def : Proc<"mips32r2", [FeatureMips32r2]>;
161 def : Proc<"mips32r6", [FeatureMips32r6]>;
163 def : Proc<"mips3", [FeatureMips3]>;
164 def : Proc<"mips4", [FeatureMips4]>;
165 def : Proc<"mips5", [FeatureMips5]>;
166 def : Proc<"mips64", [FeatureMips64]>;
167 def : Proc<"mips64r2", [FeatureMips64r2]>;
168 def : Proc<"mips64r6", [FeatureMips64r6]>;
169 def : Proc<"mips16", [FeatureMips16]>;
170 def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
172 def MipsAsmParser : AsmParser {
173 let ShouldEmitMatchRegisterName = 0;
174 let MnemonicContainsDot = 1;
177 def MipsAsmParserVariant : AsmParserVariant {
180 // Recognize hard coded registers.
181 string RegisterPrefix = "$";
185 let InstructionSet = MipsInstrInfo;
186 let AssemblyParsers = [MipsAsmParser];
187 let AssemblyParserVariants = [MipsAsmParserVariant];