lib/Target/Mips/Mips.td

   1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is the top level entry point for the Mips target.
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Target-independent interfaces
  14 //===----------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 // The overall idea of the PredicateControl class is to chop the Predicates list
  19 // into subsets that are usually overridden independently. This allows
  20 // subclasses to partially override the predicates of their superclasses without
  21 // having to re-add all the existing predicates.
  22 class PredicateControl {
  23   // Predicates for the encoding scheme in use such as HasStdEnc
  24   list<Predicate> EncodingPredicates = [];
  25   // Predicates for the GPR size such as IsGP64bit
  26   list<Predicate> GPRPredicates = [];
  27   // Predicates for the FGR size and layout such as IsFP64bit
  28   list<Predicate> FGRPredicates = [];
  29   // Predicates for the instruction group membership such as ISA's and ASE's
  30   list<Predicate> InsnPredicates = [];
  31   // Predicates for anything else
  32   list<Predicate> AdditionalPredicates = [];
  33   list<Predicate> Predicates = !listconcat(EncodingPredicates,
  34                                            GPRPredicates,
  35                                            FGRPredicates,
  36                                            InsnPredicates,
  37                                            AdditionalPredicates);
  38 }
  39
  40 // Like Requires<> but for the AdditionalPredicates list
  41 class AdditionalRequires<list<Predicate> preds> {
  42   list<Predicate> AdditionalPredicates = preds;
  43 }
  44
  45 //===----------------------------------------------------------------------===//
  46 // Register File, Calling Conv, Instruction Descriptions
  47 //===----------------------------------------------------------------------===//
  48
  49 include "MipsRegisterInfo.td"
  50 include "MipsSchedule.td"
  51 include "MipsInstrInfo.td"
  52 include "MipsCallingConv.td"
  53
  54 def MipsInstrInfo : InstrInfo;
  55
  56 //===----------------------------------------------------------------------===//
  57 // Mips Subtarget features                                                    //
  58 //===----------------------------------------------------------------------===//
  59
  60 def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
  61                                 "General Purpose Registers are 64-bit wide.">;
  62 def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
  63                                 "Support 64-bit FP registers.">;
  64 def FeatureNaN2008     : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
  65                                 "IEEE 754-2008 NaN encoding.">;
  66 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
  67                                 "true", "Only supports single precision float">;
  68 def FeatureO32         : SubtargetFeature<"o32", "MipsABI", "O32",
  69                                 "Enable o32 ABI">;
  70 def FeatureN32         : SubtargetFeature<"n32", "MipsABI", "N32",
  71                                 "Enable n32 ABI">;
  72 def FeatureN64         : SubtargetFeature<"n64", "MipsABI", "N64",
  73                                 "Enable n64 ABI">;
  74 def FeatureEABI        : SubtargetFeature<"eabi", "MipsABI", "EABI",
  75                                 "Enable eabi ABI">;
  76 def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU",
  77                                 "true", "Enable vector FPU instructions.">;
  78 def FeatureSEInReg     : SubtargetFeature<"seinreg", "HasSEInReg", "true",
  79                                 "Enable 'signext in register' instructions.">;
  80 def FeatureCondMov     : SubtargetFeature<"condmov", "HasCondMov", "true",
  81                                 "Enable 'conditional move' instructions.">;
  82 def FeatureSwap        : SubtargetFeature<"swap", "HasSwap", "true",
  83                                 "Enable 'byte/half swap' instructions.">;
  84 def FeatureBitCount    : SubtargetFeature<"bitcount", "HasBitCount", "true",
  85                                 "Enable 'count leading bits' instructions.">;
  86 def FeatureFPIdx       : SubtargetFeature<"fpidx", "HasFPIdx", "true",
  87                                 "Enable 'FP indexed load/store' instructions.">;
  88 def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
  89                                 "Mips32 ISA Support",
  90                                 [FeatureCondMov, FeatureBitCount]>;
  91 def FeatureMips32r2    : SubtargetFeature<"mips32r2", "MipsArchVersion",
  92                                 "Mips32r2", "Mips32r2 ISA Support",
  93                                 [FeatureMips32, FeatureSEInReg, FeatureSwap,
  94                                  FeatureFPIdx]>;
  95 def FeatureMips4       : SubtargetFeature<"mips4", "MipsArchVersion",
  96                                 "Mips4", "MIPS IV ISA Support",
  97                                 [FeatureGP64Bit, FeatureFP64Bit, FeatureFPIdx,
  98                                  FeatureCondMov]>;
  99 def FeatureMips64      : SubtargetFeature<"mips64", "MipsArchVersion",
 100                                 "Mips64", "Mips64 ISA Support",
 101                                 [FeatureMips4, FeatureMips32, FeatureFPIdx]>;
 102 def FeatureMips64r2    : SubtargetFeature<"mips64r2", "MipsArchVersion",
 103                                 "Mips64r2", "Mips64r2 ISA Support",
 104                                 [FeatureMips64, FeatureMips32r2]>;
 105
 106 def FeatureMips16  : SubtargetFeature<"mips16", "InMips16Mode", "true",
 107                                       "Mips16 mode">;
 108
 109 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
 110 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
 111                                     "Mips DSP-R2 ASE", [FeatureDSP]>;
 112
 113 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
 114
 115 def FeatureMicroMips  : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
 116                                          "microMips mode">;
 117
 118 def FeatureCnMips     : SubtargetFeature<"cnmips", "HasCnMips",
 119                                 "true", "Octeon cnMIPS Support",
 120                                 [FeatureMips64r2]>;
 121
 122 //===----------------------------------------------------------------------===//
 123 // Mips processors supported.
 124 //===----------------------------------------------------------------------===//
 125
 126 class Proc<string Name, list<SubtargetFeature> Features>
 127  : Processor<Name, MipsGenericItineraries, Features>;
 128
 129 def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
 130 def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
 131 def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
 132 def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
 133 def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
 134 def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
 135 def : Proc<"octeon", [FeatureMips64r2, FeatureN64, FeatureCnMips]>;
 136
 137 def MipsAsmParser : AsmParser {
 138   let ShouldEmitMatchRegisterName = 0;
 139   let MnemonicContainsDot = 1;
 140 }
 141
 142 def MipsAsmParserVariant : AsmParserVariant {
 143   int Variant = 0;
 144
 145   // Recognize hard coded registers.
 146   string RegisterPrefix = "$";
 147 }
 148
 149 def Mips : Target {
 150   let InstructionSet = MipsInstrInfo;
 151   let AssemblyParsers = [MipsAsmParser];
 152   let AssemblyParserVariants = [MipsAsmParserVariant];
 153 }