1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This is the top level entry point for the Mips target.
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 // Target-independent interfaces
14 //===----------------------------------------------------------------------===//
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // Register File, Calling Conv, Instruction Descriptions
20 //===----------------------------------------------------------------------===//
22 include "MipsRegisterInfo.td"
23 include "MipsSchedule.td"
24 include "MipsInstrInfo.td"
25 include "MipsCallingConv.td"
27 def MipsInstrInfo : InstrInfo;
29 //===----------------------------------------------------------------------===//
30 // Mips Subtarget features //
31 //===----------------------------------------------------------------------===//
33 def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
34 "General Purpose Registers are 64-bit wide.">;
35 def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
36 "Support 64-bit FP registers.">;
37 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
38 "true", "Only supports single precision float">;
39 def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
41 def FeatureN32 : SubtargetFeature<"n32", "MipsABI", "N32",
43 def FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64",
45 def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
47 def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
48 "true", "Enable vector FPU instructions.">;
49 def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true",
50 "Enable 'signext in register' instructions.">;
51 def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true",
52 "Enable 'conditional move' instructions.">;
53 def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true",
54 "Enable 'byte/half swap' instructions.">;
55 def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true",
56 "Enable 'count leading bits' instructions.">;
57 def FeatureFPIdx : SubtargetFeature<"fpidx", "HasFPIdx", "true",
58 "Enable 'FP indexed load/store' instructions.">;
59 def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
61 [FeatureCondMov, FeatureBitCount]>;
62 def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
63 "Mips32r2", "Mips32r2 ISA Support",
64 [FeatureMips32, FeatureSEInReg, FeatureSwap,
66 def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
67 "Mips4", "MIPS IV ISA Support",
68 [FeatureGP64Bit, FeatureFP64Bit, FeatureFPIdx,
70 def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
71 "Mips64", "Mips64 ISA Support",
72 [FeatureMips4, FeatureMips32, FeatureFPIdx]>;
73 def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
74 "Mips64r2", "Mips64r2 ISA Support",
75 [FeatureMips64, FeatureMips32r2]>;
77 def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
80 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
81 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
82 "Mips DSP-R2 ASE", [FeatureDSP]>;
84 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
86 def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
89 def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
90 "true", "Octeon cnMIPS Support",
93 //===----------------------------------------------------------------------===//
94 // Mips processors supported.
95 //===----------------------------------------------------------------------===//
97 class Proc<string Name, list<SubtargetFeature> Features>
98 : Processor<Name, MipsGenericItineraries, Features>;
100 def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
101 def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
102 def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
103 def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
104 def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
105 def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
106 def : Proc<"octeon", [FeatureMips64r2, FeatureN64, FeatureCnMips]>;
108 def MipsAsmParser : AsmParser {
109 let ShouldEmitMatchRegisterName = 0;
110 let MnemonicContainsDot = 1;
113 def MipsAsmParserVariant : AsmParserVariant {
116 // Recognize hard coded registers.
117 string RegisterPrefix = "$";
121 let InstructionSet = MipsInstrInfo;
122 let AssemblyParsers = [MipsAsmParser];
123 let AssemblyParserVariants = [MipsAsmParserVariant];