1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This is the top level entry point for the Mips target.
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 // Target-independent interfaces
14 //===----------------------------------------------------------------------===//
16 include "llvm/Target/Target.td"
18 // The overall idea of the PredicateControl class is to chop the Predicates list
19 // into subsets that are usually overridden independently. This allows
20 // subclasses to partially override the predicates of their superclasses without
21 // having to re-add all the existing predicates.
22 class PredicateControl {
23 // Predicates for the encoding scheme in use such as HasStdEnc
24 list<Predicate> EncodingPredicates = [];
25 // Predicates for the GPR size such as IsGP64bit
26 list<Predicate> GPRPredicates = [];
27 // Predicates for the FGR size and layout such as IsFP64bit
28 list<Predicate> FGRPredicates = [];
29 // Predicates for the instruction group membership such as ISA's and ASE's
30 list<Predicate> InsnPredicates = [];
31 // Predicate for marking the instruction as usable in hard-float mode only.
32 list<Predicate> HardFloatPredicate = [];
33 // Predicates for anything else
34 list<Predicate> AdditionalPredicates = [];
35 list<Predicate> Predicates = !listconcat(EncodingPredicates,
40 AdditionalPredicates);
43 // Like Requires<> but for the AdditionalPredicates list
44 class AdditionalRequires<list<Predicate> preds> {
45 list<Predicate> AdditionalPredicates = preds;
48 //===----------------------------------------------------------------------===//
49 // Register File, Calling Conv, Instruction Descriptions
50 //===----------------------------------------------------------------------===//
52 include "MipsRegisterInfo.td"
53 include "MipsSchedule.td"
54 include "MipsInstrInfo.td"
55 include "MipsCallingConv.td"
57 def MipsInstrInfo : InstrInfo;
59 //===----------------------------------------------------------------------===//
60 // Mips Subtarget features //
61 //===----------------------------------------------------------------------===//
63 def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true",
64 "Disable SVR4-style position-independent code">;
65 def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
66 "General Purpose Registers are 64-bit wide">;
67 def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
68 "Support 64-bit FP registers">;
69 def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true",
71 def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
72 "IEEE 754-2008 NaN encoding">;
73 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
74 "true", "Only supports single precision float">;
75 def FeatureSoftFloat : SubtargetFeature<"soft-float", "IsSoftFloat", "true",
76 "Does not support floating point instructions">;
77 def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
78 "Disable odd numbered single-precision "
80 def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
81 "true", "Enable vector FPU instructions">;
82 def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
83 "Mips I ISA Support [highly experimental]">;
84 def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
85 "Mips II ISA Support [highly experimental]",
87 def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
88 "Subset of MIPS-III that is also in MIPS32 "
89 "[highly experimental]">;
90 def FeatureMips3_32r2 : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
91 "Subset of MIPS-III that is also in MIPS32r2 "
92 "[highly experimental]">;
93 def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
94 "MIPS III ISA Support [highly experimental]",
95 [FeatureMips2, FeatureMips3_32,
96 FeatureMips3_32r2, FeatureGP64Bit,
98 def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
99 "Subset of MIPS-IV that is also in MIPS32 "
100 "[highly experimental]">;
101 def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
102 "Subset of MIPS-IV that is also in MIPS32r2 "
103 "[highly experimental]">;
104 def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
105 "Mips4", "MIPS IV ISA Support",
106 [FeatureMips3, FeatureMips4_32,
108 def FeatureMips5_32r2 : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
109 "Subset of MIPS-V that is also in MIPS32r2 "
110 "[highly experimental]">;
111 def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
112 "MIPS V ISA Support [highly experimental]",
113 [FeatureMips4, FeatureMips5_32r2]>;
114 def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
115 "Mips32 ISA Support",
116 [FeatureMips2, FeatureMips3_32,
118 def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
119 "Mips32r2", "Mips32r2 ISA Support",
120 [FeatureMips3_32r2, FeatureMips4_32r2,
121 FeatureMips5_32r2, FeatureMips32]>;
122 def FeatureMips32r3 : SubtargetFeature<"mips32r3", "MipsArchVersion",
123 "Mips32r3", "Mips32r3 ISA Support",
125 def FeatureMips32r5 : SubtargetFeature<"mips32r5", "MipsArchVersion",
126 "Mips32r5", "Mips32r5 ISA Support",
128 def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
130 "Mips32r6 ISA Support [experimental]",
131 [FeatureMips32r5, FeatureFP64Bit,
133 def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
134 "Mips64", "Mips64 ISA Support",
135 [FeatureMips5, FeatureMips32]>;
136 def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
137 "Mips64r2", "Mips64r2 ISA Support",
138 [FeatureMips64, FeatureMips32r2]>;
139 def FeatureMips64r3 : SubtargetFeature<"mips64r3", "MipsArchVersion",
140 "Mips64r3", "Mips64r3 ISA Support",
141 [FeatureMips64r2, FeatureMips32r3]>;
142 def FeatureMips64r5 : SubtargetFeature<"mips64r5", "MipsArchVersion",
143 "Mips64r5", "Mips64r5 ISA Support",
144 [FeatureMips64r3, FeatureMips32r5]>;
145 def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion",
147 "Mips64r6 ISA Support [experimental]",
148 [FeatureMips32r6, FeatureMips64r5,
151 def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
154 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
155 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
156 "Mips DSP-R2 ASE", [FeatureDSP]>;
158 : SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE",
159 [ FeatureDSP, FeatureDSPR2 ]>;
161 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
163 def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">;
165 def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
168 def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
169 "true", "Octeon cnMIPS Support",
172 def FeatureUseTCCInDIV : SubtargetFeature<
174 "UseTCCInDIV", "false",
175 "Force the assembler to use trapping">;
177 //===----------------------------------------------------------------------===//
178 // Mips processors supported.
179 //===----------------------------------------------------------------------===//
181 def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
182 "MipsSubtarget::CPU::P5600",
183 "The P5600 Processor", [FeatureMips32r5]>;
185 class Proc<string Name, list<SubtargetFeature> Features>
186 : Processor<Name, MipsGenericItineraries, Features>;
188 def : Proc<"mips1", [FeatureMips1]>;
189 def : Proc<"mips2", [FeatureMips2]>;
190 def : Proc<"mips32", [FeatureMips32]>;
191 def : Proc<"mips32r2", [FeatureMips32r2]>;
192 def : Proc<"mips32r3", [FeatureMips32r3]>;
193 def : Proc<"mips32r5", [FeatureMips32r5]>;
194 def : Proc<"mips32r6", [FeatureMips32r6]>;
196 def : Proc<"mips3", [FeatureMips3]>;
197 def : Proc<"mips4", [FeatureMips4]>;
198 def : Proc<"mips5", [FeatureMips5]>;
199 def : Proc<"mips64", [FeatureMips64]>;
200 def : Proc<"mips64r2", [FeatureMips64r2]>;
201 def : Proc<"mips64r3", [FeatureMips64r3]>;
202 def : Proc<"mips64r5", [FeatureMips64r5]>;
203 def : Proc<"mips64r6", [FeatureMips64r6]>;
204 def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
205 def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
207 def MipsAsmParser : AsmParser {
208 let ShouldEmitMatchRegisterName = 0;
209 let MnemonicContainsDot = 1;
212 def MipsAsmParserVariant : AsmParserVariant {
215 // Recognize hard coded registers.
216 string RegisterPrefix = "$";
220 let InstructionSet = MipsInstrInfo;
221 let AssemblyParsers = [MipsAsmParser];
222 let AssemblyParserVariants = [MipsAsmParserVariant];