1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This is the top level entry point for the Mips target.
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 // Target-independent interfaces
14 //===----------------------------------------------------------------------===//
16 include "llvm/Target/Target.td"
18 // The overall idea of the PredicateControl class is to chop the Predicates list
19 // into subsets that are usually overridden independently. This allows
20 // subclasses to partially override the predicates of their superclasses without
21 // having to re-add all the existing predicates.
22 class PredicateControl {
23 // Predicates for the encoding scheme in use such as HasStdEnc
24 list<Predicate> EncodingPredicates = [];
25 // Predicates for the GPR size such as IsGP64bit
26 list<Predicate> GPRPredicates = [];
27 // Predicates for the FGR size and layout such as IsFP64bit
28 list<Predicate> FGRPredicates = [];
29 // Predicates for the instruction group membership such as ISA's and ASE's
30 list<Predicate> InsnPredicates = [];
31 // Predicates for anything else
32 list<Predicate> AdditionalPredicates = [];
33 list<Predicate> Predicates = !listconcat(EncodingPredicates,
37 AdditionalPredicates);
40 // Like Requires<> but for the AdditionalPredicates list
41 class AdditionalRequires<list<Predicate> preds> {
42 list<Predicate> AdditionalPredicates = preds;
45 //===----------------------------------------------------------------------===//
46 // Register File, Calling Conv, Instruction Descriptions
47 //===----------------------------------------------------------------------===//
49 include "MipsRegisterInfo.td"
50 include "MipsSchedule.td"
51 include "MipsInstrInfo.td"
52 include "MipsCallingConv.td"
54 def MipsInstrInfo : InstrInfo;
56 //===----------------------------------------------------------------------===//
57 // Mips Subtarget features //
58 //===----------------------------------------------------------------------===//
60 def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true",
61 "Disable SVR4-style position-independent code.">;
62 def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
63 "General Purpose Registers are 64-bit wide.">;
64 def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
65 "Support 64-bit FP registers.">;
66 def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true",
68 def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
69 "IEEE 754-2008 NaN encoding.">;
70 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
71 "true", "Only supports single precision float">;
72 def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
74 def FeatureN32 : SubtargetFeature<"n32", "MipsABI", "N32",
76 def FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64",
78 def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
80 def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
81 "Disable odd numbered single-precision "
83 def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
84 "true", "Enable vector FPU instructions.">;
85 def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
86 "Mips I ISA Support [highly experimental]">;
87 def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
88 "Mips II ISA Support [highly experimental]",
90 def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
91 "Subset of MIPS-III that is also in MIPS32 "
92 "[highly experimental]">;
93 def FeatureMips3_32r2 : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
94 "Subset of MIPS-III that is also in MIPS32r2 "
95 "[highly experimental]">;
96 def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
97 "MIPS III ISA Support [highly experimental]",
98 [FeatureMips2, FeatureMips3_32,
99 FeatureMips3_32r2, FeatureGP64Bit,
101 def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
102 "Subset of MIPS-IV that is also in MIPS32 "
103 "[highly experimental]">;
104 def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
105 "Subset of MIPS-IV that is also in MIPS32r2 "
106 "[highly experimental]">;
107 def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
108 "Mips4", "MIPS IV ISA Support",
109 [FeatureMips3, FeatureMips4_32,
111 def FeatureMips5_32r2 : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
112 "Subset of MIPS-V that is also in MIPS32r2 "
113 "[highly experimental]">;
114 def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
115 "MIPS V ISA Support [highly experimental]",
116 [FeatureMips4, FeatureMips5_32r2]>;
117 def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
118 "Mips32 ISA Support",
119 [FeatureMips2, FeatureMips3_32,
121 def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
122 "Mips32r2", "Mips32r2 ISA Support",
123 [FeatureMips3_32r2, FeatureMips4_32r2,
124 FeatureMips5_32r2, FeatureMips32]>;
125 def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
127 "Mips32r6 ISA Support [experimental]",
128 [FeatureMips32r2, FeatureFP64Bit,
130 def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
131 "Mips64", "Mips64 ISA Support",
132 [FeatureMips5, FeatureMips32]>;
133 def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
134 "Mips64r2", "Mips64r2 ISA Support",
135 [FeatureMips64, FeatureMips32r2]>;
136 def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion",
138 "Mips64r6 ISA Support [experimental]",
139 [FeatureMips32r6, FeatureMips64r2,
142 def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
145 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
146 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
147 "Mips DSP-R2 ASE", [FeatureDSP]>;
149 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
151 def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
154 def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
155 "true", "Octeon cnMIPS Support",
158 //===----------------------------------------------------------------------===//
159 // Mips processors supported.
160 //===----------------------------------------------------------------------===//
162 class Proc<string Name, list<SubtargetFeature> Features>
163 : Processor<Name, MipsGenericItineraries, Features>;
165 def : Proc<"mips1", [FeatureMips1, FeatureO32]>;
166 def : Proc<"mips2", [FeatureMips2, FeatureO32]>;
167 def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
168 def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
169 def : Proc<"mips32r6", [FeatureMips32r6, FeatureO32]>;
171 def : Proc<"mips3", [FeatureMips3, FeatureN64]>;
172 def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
173 def : Proc<"mips5", [FeatureMips5, FeatureN64]>;
174 def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
175 def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
176 def : Proc<"mips64r6", [FeatureMips64r6, FeatureN64]>;
177 def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
178 def : Proc<"octeon", [FeatureMips64r2, FeatureN64, FeatureCnMips]>;
180 def MipsAsmParser : AsmParser {
181 let ShouldEmitMatchRegisterName = 0;
182 let MnemonicContainsDot = 1;
185 def MipsAsmParserVariant : AsmParserVariant {
188 // Recognize hard coded registers.
189 string RegisterPrefix = "$";
193 let InstructionSet = MipsInstrInfo;
194 let AssemblyParsers = [MipsAsmParser];
195 let AssemblyParserVariants = [MipsAsmParserVariant];