lib/Target/Mips/Mips.td

   1 //===- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===---------------------------------------------------------------------===//
   9 // This is the top level entry point for the Mips target.
  10 //===---------------------------------------------------------------------===//
  11
  12 //===---------------------------------------------------------------------===//
  13 // Target-independent interfaces
  14 //===---------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 //===---------------------------------------------------------------------===//
  19 // Register File, Calling Conv, Instruction Descriptions
  20 //===---------------------------------------------------------------------===//
  21
  22 include "MipsRegisterInfo.td"
  23 include "MipsSchedule.td"
  24 include "MipsInstrInfo.td"
  25 include "MipsCallingConv.td"
  26
  27 def MipsInstrInfo : InstrInfo;
  28
  29 //===---------------------------------------------------------------------===//
  30 // Mips Subtarget features                                                   //
  31 //===---------------------------------------------------------------------===//
  32
  33 def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
  34                                 "General Purpose Registers are 64-bit wide.">;
  35 def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
  36                                 "Support 64-bit FP registers.">;
  37 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
  38                                 "true",
  39                                 "Only supports single precision float">;
  40 def FeatureO32         : SubtargetFeature<"o32", "MipsABI", "O32",
  41                                 "Enable o32 ABI">;
  42 def FeatureEABI        : SubtargetFeature<"eabi", "MipsABI", "EABI",
  43                                 "Enable eabi ABI">;
  44 def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU",
  45                                 "true", "Enable vector FPU instructions.">;
  46 def FeatureSEInReg     : SubtargetFeature<"seinreg", "HasSEInReg", "true",
  47                                 "Enable 'signext in register' instructions.">;
  48 def FeatureCondMov     : SubtargetFeature<"condmov", "HasCondMov", "true",
  49                                 "Enable 'conditional move' instructions.">;
  50 def FeatureMulDivAdd   : SubtargetFeature<"muldivadd", "HasMulDivAdd", "true",
  51                                 "Enable 'multiply add/sub' instructions.">;
  52 def FeatureMinMax      : SubtargetFeature<"minmax", "HasMinMax", "true",
  53                                 "Enable 'min/max' instructions.">;
  54 def FeatureSwap        : SubtargetFeature<"swap", "HasSwap", "true",
  55                                 "Enable 'byte/half swap' instructions.">;
  56 def FeatureBitCount    : SubtargetFeature<"bitcount", "HasBitCount", "true",
  57                                 "Enable 'count leading bits' instructions.">;
  58 def FeatureMips1       : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
  59                                 "Mips1 ISA Support">;
  60 def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
  61                                 "Mips2 ISA Support">;
  62 def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion",
  63                                 "Mips32", "Mips32 ISA Support",
  64                                 [FeatureCondMov, FeatureBitCount]>;
  65 def FeatureMips32r2    : SubtargetFeature<"mips32r2", "MipsArchVersion",
  66                                 "Mips32r2", "Mips32r2 ISA Support",
  67                                 [FeatureMips32, FeatureSEInReg]>;
  68
  69 //===---------------------------------------------------------------------===//
  70 // Mips processors supported.
  71 //===---------------------------------------------------------------------===//
  72
  73 class Proc<string Name, list<SubtargetFeature> Features>
  74  : Processor<Name, MipsGenericItineraries, Features>;
  75
  76 def : Proc<"mips1", [FeatureMips1]>;
  77 def : Proc<"r2000", [FeatureMips1]>;
  78 def : Proc<"r3000", [FeatureMips1]>;
  79
  80 def : Proc<"mips2", [FeatureMips2]>;
  81 def : Proc<"r6000", [FeatureMips2]>;
  82
  83 def : Proc<"4ke", [FeatureMips32r2]>;
  84
  85 // Allegrex is a 32bit subset of r4000, both for integer and fp registers,
  86 // but much more similar to Mips2 than Mips3. It also contains some of
  87 // Mips32/Mips32r2 instructions and a custom vector fpu processor.
  88 def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI,
  89       FeatureVFPU, FeatureSEInReg, FeatureCondMov, FeatureMulDivAdd,
  90       FeatureMinMax, FeatureSwap, FeatureBitCount]>;
  91
  92 def Mips : Target {
  93   let InstructionSet = MipsInstrInfo;
  94 }