lib/Target/Mips/Mips.td

   1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is the top level entry point for the Mips target.
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Target-independent interfaces
  14 //===----------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // Register File, Calling Conv, Instruction Descriptions
  20 //===----------------------------------------------------------------------===//
  21
  22 include "MipsRegisterInfo.td"
  23 include "MipsSchedule.td"
  24 include "MipsInstrInfo.td"
  25 include "MipsCallingConv.td"
  26
  27 def MipsInstrInfo : InstrInfo;
  28
  29 //===----------------------------------------------------------------------===//
  30 // Mips Subtarget features                                                    //
  31 //===----------------------------------------------------------------------===//
  32
  33 def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
  34                                 "General Purpose Registers are 64-bit wide.">;
  35 def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
  36                                 "Support 64-bit FP registers.">;
  37 def FeatureNaN2008     : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
  38                                 "IEEE 754-2008 NaN encoding.">;
  39 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
  40                                 "true", "Only supports single precision float">;
  41 def FeatureO32         : SubtargetFeature<"o32", "MipsABI", "O32",
  42                                 "Enable o32 ABI">;
  43 def FeatureN32         : SubtargetFeature<"n32", "MipsABI", "N32",
  44                                 "Enable n32 ABI">;
  45 def FeatureN64         : SubtargetFeature<"n64", "MipsABI", "N64",
  46                                 "Enable n64 ABI">;
  47 def FeatureEABI        : SubtargetFeature<"eabi", "MipsABI", "EABI",
  48                                 "Enable eabi ABI">;
  49 def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU",
  50                                 "true", "Enable vector FPU instructions.">;
  51 def FeatureSEInReg     : SubtargetFeature<"seinreg", "HasSEInReg", "true",
  52                                 "Enable 'signext in register' instructions.">;
  53 def FeatureCondMov     : SubtargetFeature<"condmov", "HasCondMov", "true",
  54                                 "Enable 'conditional move' instructions.">;
  55 def FeatureSwap        : SubtargetFeature<"swap", "HasSwap", "true",
  56                                 "Enable 'byte/half swap' instructions.">;
  57 def FeatureBitCount    : SubtargetFeature<"bitcount", "HasBitCount", "true",
  58                                 "Enable 'count leading bits' instructions.">;
  59 def FeatureFPIdx       : SubtargetFeature<"fpidx", "HasFPIdx", "true",
  60                                 "Enable 'FP indexed load/store' instructions.">;
  61 def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
  62                                 "Mips32 ISA Support",
  63                                 [FeatureCondMov, FeatureBitCount]>;
  64 def FeatureMips32r2    : SubtargetFeature<"mips32r2", "MipsArchVersion",
  65                                 "Mips32r2", "Mips32r2 ISA Support",
  66                                 [FeatureMips32, FeatureSEInReg, FeatureSwap,
  67                                  FeatureFPIdx]>;
  68 def FeatureMips4       : SubtargetFeature<"mips4", "MipsArchVersion",
  69                                 "Mips4", "MIPS IV ISA Support",
  70                                 [FeatureGP64Bit, FeatureFP64Bit, FeatureFPIdx,
  71                                  FeatureCondMov]>;
  72 def FeatureMips64      : SubtargetFeature<"mips64", "MipsArchVersion",
  73                                 "Mips64", "Mips64 ISA Support",
  74                                 [FeatureMips4, FeatureMips32, FeatureFPIdx]>;
  75 def FeatureMips64r2    : SubtargetFeature<"mips64r2", "MipsArchVersion",
  76                                 "Mips64r2", "Mips64r2 ISA Support",
  77                                 [FeatureMips64, FeatureMips32r2]>;
  78
  79 def FeatureMips16  : SubtargetFeature<"mips16", "InMips16Mode", "true",
  80                                       "Mips16 mode">;
  81
  82 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
  83 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
  84                                     "Mips DSP-R2 ASE", [FeatureDSP]>;
  85
  86 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
  87
  88 def FeatureMicroMips  : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
  89                                          "microMips mode">;
  90
  91 def FeatureCnMips     : SubtargetFeature<"cnmips", "HasCnMips",
  92                                 "true", "Octeon cnMIPS Support",
  93                                 [FeatureMips64r2]>;
  94
  95 //===----------------------------------------------------------------------===//
  96 // Mips processors supported.
  97 //===----------------------------------------------------------------------===//
  98
  99 class Proc<string Name, list<SubtargetFeature> Features>
 100  : Processor<Name, MipsGenericItineraries, Features>;
 101
 102 def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
 103 def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
 104 def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
 105 def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
 106 def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
 107 def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
 108 def : Proc<"octeon", [FeatureMips64r2, FeatureN64, FeatureCnMips]>;
 109
 110 def MipsAsmParser : AsmParser {
 111   let ShouldEmitMatchRegisterName = 0;
 112   let MnemonicContainsDot = 1;
 113 }
 114
 115 def MipsAsmParserVariant : AsmParserVariant {
 116   int Variant = 0;
 117
 118   // Recognize hard coded registers.
 119   string RegisterPrefix = "$";
 120 }
 121
 122 def Mips : Target {
 123   let InstructionSet = MipsInstrInfo;
 124   let AssemblyParsers = [MipsAsmParser];
 125   let AssemblyParserVariants = [MipsAsmParserVariant];
 126 }