1 //===- Mips.td - Describe the Mips Target Machine ----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This is the top level entry point for the Mips target.
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 // Target-independent interfaces
14 //===----------------------------------------------------------------------===//
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // Register File, Calling Conv, Instruction Descriptions
20 //===----------------------------------------------------------------------===//
22 include "MipsRegisterInfo.td"
23 include "MipsSchedule.td"
24 include "MipsInstrInfo.td"
25 include "MipsCallingConv.td"
27 def MipsInstrInfo : InstrInfo;
29 //===----------------------------------------------------------------------===//
30 // Mips Subtarget features //
31 //===----------------------------------------------------------------------===//
33 def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
34 "General Purpose Registers are 64-bit wide.">;
35 def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
36 "Support 64-bit FP registers.">;
37 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
38 "true", "Only supports single precision float">;
39 def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
41 def FeatureN32 : SubtargetFeature<"n32", "MipsABI", "N32",
43 def FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64",
45 def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
47 def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
48 "true", "Enable vector FPU instructions.">;
49 def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true",
50 "Enable 'signext in register' instructions.">;
51 def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true",
52 "Enable 'conditional move' instructions.">;
53 def FeatureMulDivAdd : SubtargetFeature<"muldivadd", "HasMulDivAdd", "true",
54 "Enable 'multiply add/sub' instructions.">;
55 def FeatureMinMax : SubtargetFeature<"minmax", "HasMinMax", "true",
56 "Enable 'min/max' instructions.">;
57 def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true",
58 "Enable 'byte/half swap' instructions.">;
59 def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true",
60 "Enable 'count leading bits' instructions.">;
61 def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
63 [FeatureCondMov, FeatureBitCount]>;
64 def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
65 "Mips32r2", "Mips32r2 ISA Support",
66 [FeatureMips32, FeatureSEInReg, FeatureSwap]>;
67 def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
68 "Mips64", "Mips64 ISA Support",
69 [FeatureGP64Bit, FeatureFP64Bit,
71 def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
72 "Mips64r2", "Mips64r2 ISA Support",
73 [FeatureMips64, FeatureMips32r2]>;
75 //===----------------------------------------------------------------------===//
76 // Mips processors supported.
77 //===----------------------------------------------------------------------===//
79 class Proc<string Name, list<SubtargetFeature> Features>
80 : Processor<Name, MipsGenericItineraries, Features>;
82 def : Proc<"mips32", [FeatureMips32]>;
83 def : Proc<"mips32r2", [FeatureMips32r2]>;
84 def : Proc<"mips64", [FeatureMips64]>;
85 def : Proc<"mips64r2", [FeatureMips64r2]>;
87 def MipsAsmWriter : AsmWriter {
88 string AsmWriterClassName = "InstPrinter";
89 bit isMCAsmWriter = 1;
93 let InstructionSet = MipsInstrInfo;
95 let AssemblyWriters = [MipsAsmWriter];