1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This is the top level entry point for the Mips target.
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 // Target-independent interfaces
14 //===----------------------------------------------------------------------===//
16 include "llvm/Target/Target.td"
18 // The overall idea of the PredicateControl class is to chop the Predicates list
19 // into subsets that are usually overridden independently. This allows
20 // subclasses to partially override the predicates of their superclasses without
21 // having to re-add all the existing predicates.
22 class PredicateControl {
23 // Predicates for the encoding scheme in use such as HasStdEnc
24 list<Predicate> EncodingPredicates = [];
25 // Predicates for the GPR size such as IsGP64bit
26 list<Predicate> GPRPredicates = [];
27 // Predicates for the FGR size and layout such as IsFP64bit
28 list<Predicate> FGRPredicates = [];
29 // Predicates for the instruction group membership such as ISA's and ASE's
30 list<Predicate> InsnPredicates = [];
31 // Predicates for anything else
32 list<Predicate> AdditionalPredicates = [];
33 list<Predicate> Predicates = !listconcat(EncodingPredicates,
37 AdditionalPredicates);
40 // Like Requires<> but for the AdditionalPredicates list
41 class AdditionalRequires<list<Predicate> preds> {
42 list<Predicate> AdditionalPredicates = preds;
45 //===----------------------------------------------------------------------===//
46 // Register File, Calling Conv, Instruction Descriptions
47 //===----------------------------------------------------------------------===//
49 include "MipsRegisterInfo.td"
50 include "MipsSchedule.td"
51 include "MipsInstrInfo.td"
52 include "MipsCallingConv.td"
54 def MipsInstrInfo : InstrInfo;
56 //===----------------------------------------------------------------------===//
57 // Mips Subtarget features //
58 //===----------------------------------------------------------------------===//
60 def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
61 "General Purpose Registers are 64-bit wide.">;
62 def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
63 "Support 64-bit FP registers.">;
64 def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
65 "IEEE 754-2008 NaN encoding.">;
66 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
67 "true", "Only supports single precision float">;
68 def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
70 def FeatureN32 : SubtargetFeature<"n32", "MipsABI", "N32",
72 def FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64",
74 def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
76 def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
77 "true", "Enable vector FPU instructions.">;
78 def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true",
79 "Enable 'signext in register' instructions.">;
80 def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true",
81 "Enable 'byte/half swap' instructions.">;
82 def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true",
83 "Enable 'count leading bits' instructions.">;
84 def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
85 "Mips I ISA Support [highly experimental]">;
86 def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
87 "Mips II ISA Support [highly experimental]",
89 def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
90 "Subset of MIPS-III that is also in MIPS32 "
91 "[highly experimental]">;
92 def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
93 "MIPS III ISA Support [highly experimental]",
94 [FeatureMips2, FeatureMips3_32,
95 FeatureGP64Bit, FeatureFP64Bit]>;
96 def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
97 "Subset of MIPS-IV that is also in MIPS32 "
98 "[highly experimental]">;
99 def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
100 "Subset of MIPS-IV that is also in MIPS32r2 "
101 "[highly experimental]">;
102 def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
103 "Mips4", "MIPS IV ISA Support",
104 [FeatureMips3, FeatureMips4_32,
106 def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
107 "MIPS V ISA Support [highly experimental]",
109 def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
110 "Mips32 ISA Support",
111 [FeatureMips2, FeatureMips3_32,
112 FeatureMips4_32, FeatureBitCount]>;
113 def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
114 "Mips32r2", "Mips32r2 ISA Support",
115 [FeatureMips4_32r2, FeatureMips32,
116 FeatureSEInReg, FeatureSwap]>;
117 def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
119 "Mips32r6 ISA Support [experimental]",
120 [FeatureMips32r2, FeatureFP64Bit,
122 def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
123 "Mips64", "Mips64 ISA Support",
124 [FeatureMips5, FeatureMips32]>;
125 def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
126 "Mips64r2", "Mips64r2 ISA Support",
127 [FeatureMips64, FeatureMips32r2]>;
128 def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion",
130 "Mips64r6 ISA Support [experimental]",
131 [FeatureMips64r2, FeatureNaN2008]>;
133 def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
136 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
137 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
138 "Mips DSP-R2 ASE", [FeatureDSP]>;
140 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
142 def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
145 def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
146 "true", "Octeon cnMIPS Support",
149 //===----------------------------------------------------------------------===//
150 // Mips processors supported.
151 //===----------------------------------------------------------------------===//
153 class Proc<string Name, list<SubtargetFeature> Features>
154 : Processor<Name, MipsGenericItineraries, Features>;
156 def : Proc<"mips1", [FeatureMips1, FeatureO32]>;
157 def : Proc<"mips2", [FeatureMips2, FeatureO32]>;
158 def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
159 def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
160 def : Proc<"mips32r6", [FeatureMips32r6, FeatureO32]>;
162 def : Proc<"mips3", [FeatureMips3, FeatureN64]>;
163 def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
164 def : Proc<"mips5", [FeatureMips5, FeatureN64]>;
165 def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
166 def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
167 def : Proc<"mips64r6", [FeatureMips64r6, FeatureN64]>;
168 def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
169 def : Proc<"octeon", [FeatureMips64r2, FeatureN64, FeatureCnMips]>;
171 def MipsAsmParser : AsmParser {
172 let ShouldEmitMatchRegisterName = 0;
173 let MnemonicContainsDot = 1;
176 def MipsAsmParserVariant : AsmParserVariant {
179 // Recognize hard coded registers.
180 string RegisterPrefix = "$";
184 let InstructionSet = MipsInstrInfo;
185 let AssemblyParsers = [MipsAsmParser];
186 let AssemblyParserVariants = [MipsAsmParserVariant];