1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This is the top level entry point for the Mips target.
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 // Target-independent interfaces
14 //===----------------------------------------------------------------------===//
16 include "llvm/Target/Target.td"
18 // The overall idea of the PredicateControl class is to chop the Predicates list
19 // into subsets that are usually overridden independently. This allows
20 // subclasses to partially override the predicates of their superclasses without
21 // having to re-add all the existing predicates.
22 class PredicateControl {
23 // Predicates for the encoding scheme in use such as HasStdEnc
24 list<Predicate> EncodingPredicates = [];
25 // Predicates for the GPR size such as IsGP64bit
26 list<Predicate> GPRPredicates = [];
27 // Predicates for the FGR size and layout such as IsFP64bit
28 list<Predicate> FGRPredicates = [];
29 // Predicates for anything else
30 list<Predicate> AdditionalPredicates = [];
31 list<Predicate> Predicates = !listconcat(EncodingPredicates,
34 AdditionalPredicates);
37 // Like Requires<> but for the AdditionalPredicates list
38 class AdditionalRequires<list<Predicate> preds> {
39 list<Predicate> AdditionalPredicates = preds;
42 //===----------------------------------------------------------------------===//
43 // Register File, Calling Conv, Instruction Descriptions
44 //===----------------------------------------------------------------------===//
46 include "MipsRegisterInfo.td"
47 include "MipsSchedule.td"
48 include "MipsInstrInfo.td"
49 include "MipsCallingConv.td"
51 def MipsInstrInfo : InstrInfo;
53 //===----------------------------------------------------------------------===//
54 // Mips Subtarget features //
55 //===----------------------------------------------------------------------===//
57 def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
58 "General Purpose Registers are 64-bit wide.">;
59 def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
60 "Support 64-bit FP registers.">;
61 def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
62 "IEEE 754-2008 NaN encoding.">;
63 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
64 "true", "Only supports single precision float">;
65 def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
67 def FeatureN32 : SubtargetFeature<"n32", "MipsABI", "N32",
69 def FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64",
71 def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
73 def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
74 "true", "Enable vector FPU instructions.">;
75 def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true",
76 "Enable 'signext in register' instructions.">;
77 def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true",
78 "Enable 'conditional move' instructions.">;
79 def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true",
80 "Enable 'byte/half swap' instructions.">;
81 def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true",
82 "Enable 'count leading bits' instructions.">;
83 def FeatureFPIdx : SubtargetFeature<"fpidx", "HasFPIdx", "true",
84 "Enable 'FP indexed load/store' instructions.">;
85 def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
87 [FeatureCondMov, FeatureBitCount]>;
88 def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
89 "Mips32r2", "Mips32r2 ISA Support",
90 [FeatureMips32, FeatureSEInReg, FeatureSwap,
92 def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
93 "Mips4", "MIPS IV ISA Support",
94 [FeatureGP64Bit, FeatureFP64Bit, FeatureFPIdx,
96 def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
97 "Mips64", "Mips64 ISA Support",
98 [FeatureMips4, FeatureMips32, FeatureFPIdx]>;
99 def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
100 "Mips64r2", "Mips64r2 ISA Support",
101 [FeatureMips64, FeatureMips32r2]>;
103 def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
106 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
107 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
108 "Mips DSP-R2 ASE", [FeatureDSP]>;
110 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
112 def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
115 def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
116 "true", "Octeon cnMIPS Support",
119 //===----------------------------------------------------------------------===//
120 // Mips processors supported.
121 //===----------------------------------------------------------------------===//
123 class Proc<string Name, list<SubtargetFeature> Features>
124 : Processor<Name, MipsGenericItineraries, Features>;
126 def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
127 def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
128 def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
129 def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
130 def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
131 def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
132 def : Proc<"octeon", [FeatureMips64r2, FeatureN64, FeatureCnMips]>;
134 def MipsAsmParser : AsmParser {
135 let ShouldEmitMatchRegisterName = 0;
136 let MnemonicContainsDot = 1;
139 def MipsAsmParserVariant : AsmParserVariant {
142 // Recognize hard coded registers.
143 string RegisterPrefix = "$";
147 let InstructionSet = MipsInstrInfo;
148 let AssemblyParsers = [MipsAsmParser];
149 let AssemblyParserVariants = [MipsAsmParserVariant];