1 //===-- Mips16FrameLowering.cpp - Mips16 Frame Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips16 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "Mips16FrameLowering.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "Mips16InstrInfo.h"
17 #include "MipsInstrInfo.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Target/TargetOptions.h"
32 Mips16FrameLowering::Mips16FrameLowering(const MipsSubtarget &STI)
33 : MipsFrameLowering(STI, STI.stackAlignment()) {}
35 void Mips16FrameLowering::emitPrologue(MachineFunction &MF,
36 MachineBasicBlock &MBB) const {
37 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
38 MachineFrameInfo *MFI = MF.getFrameInfo();
39 const Mips16InstrInfo &TII =
40 *static_cast<const Mips16InstrInfo *>(STI.getInstrInfo());
41 MachineBasicBlock::iterator MBBI = MBB.begin();
42 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
43 uint64_t StackSize = MFI->getStackSize();
45 // No need to allocate space on the stack.
46 if (StackSize == 0 && !MFI->adjustsStack()) return;
48 MachineModuleInfo &MMI = MF.getMMI();
49 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
50 MachineLocation DstML, SrcML;
53 TII.makeFrame(Mips::SP, StackSize, MBB, MBBI);
55 // emit ".cfi_def_cfa_offset StackSize"
56 unsigned CFIIndex = MMI.addFrameInst(
57 MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
58 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
59 .addCFIIndex(CFIIndex);
61 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
64 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
66 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
67 E = CSI.end(); I != E; ++I) {
68 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
69 unsigned Reg = I->getReg();
70 unsigned DReg = MRI->getDwarfRegNum(Reg, true);
71 unsigned CFIIndex = MMI.addFrameInst(
72 MCCFIInstruction::createOffset(nullptr, DReg, Offset));
73 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
74 .addCFIIndex(CFIIndex);
78 BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
79 .addReg(Mips::SP).setMIFlag(MachineInstr::FrameSetup);
83 void Mips16FrameLowering::emitEpilogue(MachineFunction &MF,
84 MachineBasicBlock &MBB) const {
85 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
86 MachineFrameInfo *MFI = MF.getFrameInfo();
87 const Mips16InstrInfo &TII =
88 *static_cast<const Mips16InstrInfo *>(STI.getInstrInfo());
89 DebugLoc dl = MBBI->getDebugLoc();
90 uint64_t StackSize = MFI->getStackSize();
96 BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP)
100 // assumes stacksize multiple of 8
101 TII.restoreFrame(Mips::SP, StackSize, MBB, MBBI);
104 bool Mips16FrameLowering::
105 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
106 MachineBasicBlock::iterator MI,
107 const std::vector<CalleeSavedInfo> &CSI,
108 const TargetRegisterInfo *TRI) const {
109 MachineFunction *MF = MBB.getParent();
110 MachineBasicBlock *EntryBlock = MF->begin();
113 // Registers RA, S0,S1 are the callee saved registers and they
114 // will be saved with the "save" instruction
115 // during emitPrologue
117 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
118 // Add the callee-saved register as live-in. Do not add if the register is
119 // RA and return address is taken, because it has already been added in
120 // method MipsTargetLowering::LowerRETURNADDR.
121 // It's killed at the spill, unless the register is RA and return address
123 unsigned Reg = CSI[i].getReg();
124 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA)
125 && MF->getFrameInfo()->isReturnAddressTaken();
126 if (!IsRAAndRetAddrIsTaken)
127 EntryBlock->addLiveIn(Reg);
133 bool Mips16FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
134 MachineBasicBlock::iterator MI,
135 const std::vector<CalleeSavedInfo> &CSI,
136 const TargetRegisterInfo *TRI) const {
138 // Registers RA,S0,S1 are the callee saved registers and they will be restored
139 // with the restore instruction during emitEpilogue.
140 // We need to override this virtual function, otherwise llvm will try and
141 // restore the registers on it's on from the stack.
148 Mips16FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
149 const MachineFrameInfo *MFI = MF.getFrameInfo();
150 // Reserve call frame if the size of the maximum call frame fits into 15-bit
151 // immediate field and there are no variable sized objects on the stack.
152 return isInt<15>(MFI->getMaxCallFrameSize()) && !MFI->hasVarSizedObjects();
155 void Mips16FrameLowering::determineCalleeSaves(MachineFunction &MF,
156 BitVector &SavedRegs,
157 RegScavenger *RS) const {
158 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
159 const Mips16InstrInfo &TII =
160 *static_cast<const Mips16InstrInfo *>(STI.getInstrInfo());
161 const MipsRegisterInfo &RI = TII.getRegisterInfo();
162 const BitVector Reserved = RI.getReservedRegs(MF);
163 bool SaveS2 = Reserved[Mips::S2];
165 SavedRegs.set(Mips::S2);
167 SavedRegs.set(Mips::S0);
170 const MipsFrameLowering *
171 llvm::createMips16FrameLowering(const MipsSubtarget &ST) {
172 return new Mips16FrameLowering(ST);