1 //===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips16.
12 //===----------------------------------------------------------------------===//
13 #define DEBUG_TYPE "mips-lower"
14 #include "Mips16ISelLowering.h"
15 #include "MipsRegisterInfo.h"
16 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Target/TargetInstrInfo.h"
25 Mips16HardFloat("mips16-hard-float", cl::NotHidden,
26 cl::desc("MIPS: mips16 hard float enable."),
29 static cl::opt<bool> DontExpandCondPseudos16(
30 "mips16-dont-expand-cond-pseudo",
32 cl::desc("Dont expand conditional move related "
33 "pseudos for Mips 16"),
37 std::set<const char*, MipsTargetLowering::LTStr> NoHelperNeeded;
40 Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM)
41 : MipsTargetLowering(TM) {
43 // set up as if mips32 and then revert so we can test the mechanism
45 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
46 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
47 computeRegisterProperties();
48 clearRegisterClasses();
50 // Set up the register classes
51 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
54 setMips16HardFloatLibCalls();
56 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
57 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
58 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
59 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
60 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
61 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
62 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
63 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
64 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
65 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
66 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
67 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
68 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
69 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
71 computeRegisterProperties();
74 const MipsTargetLowering *
75 llvm::createMips16TargetLowering(MipsTargetMachine &TM) {
76 return new Mips16TargetLowering(TM);
80 Mips16TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
85 Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
86 MachineBasicBlock *BB) const {
87 switch (MI->getOpcode()) {
89 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
91 return emitSel16(Mips::BeqzRxImm16, MI, BB);
93 return emitSel16(Mips::BnezRxImm16, MI, BB);
94 case Mips::SelTBteqZCmpi:
95 return emitSeliT16(Mips::BteqzX16, Mips::CmpiRxImmX16, MI, BB);
96 case Mips::SelTBteqZSlti:
97 return emitSeliT16(Mips::BteqzX16, Mips::SltiRxImmX16, MI, BB);
98 case Mips::SelTBteqZSltiu:
99 return emitSeliT16(Mips::BteqzX16, Mips::SltiuRxImmX16, MI, BB);
100 case Mips::SelTBtneZCmpi:
101 return emitSeliT16(Mips::BtnezX16, Mips::CmpiRxImmX16, MI, BB);
102 case Mips::SelTBtneZSlti:
103 return emitSeliT16(Mips::BtnezX16, Mips::SltiRxImmX16, MI, BB);
104 case Mips::SelTBtneZSltiu:
105 return emitSeliT16(Mips::BtnezX16, Mips::SltiuRxImmX16, MI, BB);
106 case Mips::SelTBteqZCmp:
107 return emitSelT16(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
108 case Mips::SelTBteqZSlt:
109 return emitSelT16(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
110 case Mips::SelTBteqZSltu:
111 return emitSelT16(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
112 case Mips::SelTBtneZCmp:
113 return emitSelT16(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
114 case Mips::SelTBtneZSlt:
115 return emitSelT16(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
116 case Mips::SelTBtneZSltu:
117 return emitSelT16(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
118 case Mips::BteqzT8CmpX16:
119 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
120 case Mips::BteqzT8SltX16:
121 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
122 case Mips::BteqzT8SltuX16:
123 // TBD: figure out a way to get this or remove the instruction
125 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
126 case Mips::BtnezT8CmpX16:
127 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
128 case Mips::BtnezT8SltX16:
129 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
130 case Mips::BtnezT8SltuX16:
131 // TBD: figure out a way to get this or remove the instruction
133 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
134 case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins(
135 Mips::BteqzX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, MI, BB);
136 case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins(
137 Mips::BteqzX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
138 case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins(
139 Mips::BteqzX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
140 case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins(
141 Mips::BtnezX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, MI, BB);
142 case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins(
143 Mips::BtnezX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
144 case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins(
145 Mips::BtnezX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
147 case Mips::SltCCRxRy16:
148 return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
150 case Mips::SltiCCRxImmX16:
151 return emitFEXT_CCRXI16_ins
152 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
153 case Mips::SltiuCCRxImmX16:
154 return emitFEXT_CCRXI16_ins
155 (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
156 case Mips::SltuCCRxRy16:
157 return emitFEXT_CCRX16_ins
158 (Mips::SltuRxRy16, MI, BB);
162 bool Mips16TargetLowering::
163 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
164 unsigned NextStackOffset,
165 const MipsFunctionInfo& FI) const {
166 // No tail call optimization for mips16.
170 void Mips16TargetLowering::setMips16LibcallName
171 (RTLIB::Libcall L, const char *Name) {
172 setLibcallName(L, Name);
173 NoHelperNeeded.insert(Name);
176 void Mips16TargetLowering::setMips16HardFloatLibCalls() {
177 setMips16LibcallName(RTLIB::ADD_F32, "__mips16_addsf3");
178 setMips16LibcallName(RTLIB::ADD_F64, "__mips16_adddf3");
179 setMips16LibcallName(RTLIB::SUB_F32, "__mips16_subsf3");
180 setMips16LibcallName(RTLIB::SUB_F64, "__mips16_subdf3");
181 setMips16LibcallName(RTLIB::MUL_F32, "__mips16_mulsf3");
182 setMips16LibcallName(RTLIB::MUL_F64, "__mips16_muldf3");
183 setMips16LibcallName(RTLIB::DIV_F32, "__mips16_divsf3");
184 setMips16LibcallName(RTLIB::DIV_F64, "__mips16_divdf3");
185 setMips16LibcallName(RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2");
186 setMips16LibcallName(RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2");
187 setMips16LibcallName(RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi");
188 setMips16LibcallName(RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi");
189 setMips16LibcallName(RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf");
190 setMips16LibcallName(RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf");
191 setMips16LibcallName(RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf");
192 setMips16LibcallName(RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf");
193 setMips16LibcallName(RTLIB::OEQ_F32, "__mips16_eqsf2");
194 setMips16LibcallName(RTLIB::OEQ_F64, "__mips16_eqdf2");
195 setMips16LibcallName(RTLIB::UNE_F32, "__mips16_nesf2");
196 setMips16LibcallName(RTLIB::UNE_F64, "__mips16_nedf2");
197 setMips16LibcallName(RTLIB::OGE_F32, "__mips16_gesf2");
198 setMips16LibcallName(RTLIB::OGE_F64, "__mips16_gedf2");
199 setMips16LibcallName(RTLIB::OLT_F32, "__mips16_ltsf2");
200 setMips16LibcallName(RTLIB::OLT_F64, "__mips16_ltdf2");
201 setMips16LibcallName(RTLIB::OLE_F32, "__mips16_lesf2");
202 setMips16LibcallName(RTLIB::OLE_F64, "__mips16_ledf2");
203 setMips16LibcallName(RTLIB::OGT_F32, "__mips16_gtsf2");
204 setMips16LibcallName(RTLIB::OGT_F64, "__mips16_gtdf2");
205 setMips16LibcallName(RTLIB::UO_F32, "__mips16_unordsf2");
206 setMips16LibcallName(RTLIB::UO_F64, "__mips16_unorddf2");
207 setMips16LibcallName(RTLIB::O_F32, "__mips16_unordsf2");
208 setMips16LibcallName(RTLIB::O_F64, "__mips16_unorddf2");
213 // The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
214 // cleaner way to do all of this but it will have to wait until the traditional
215 // gcc mechanism is completed.
217 // For Pic, in order for Mips16 code to call Mips32 code which according the abi
218 // have either arguments or returned values placed in floating point registers,
219 // we use a set of helper functions. (This includes functions which return type
220 // complex which on Mips are returned in a pair of floating point registers).
222 // This is an encoding that we inherited from gcc.
223 // In Mips traditional O32, N32 ABI, floating point numbers are passed in
224 // floating point argument registers 1,2 only when the first and optionally
225 // the second arguments are float (sf) or double (df).
226 // For Mips16 we are only concerned with the situations where floating point
227 // arguments are being passed in floating point registers by the ABI, because
228 // Mips16 mode code cannot execute floating point instructions to load those
229 // values and hence helper functions are needed.
230 // The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
231 // the helper function suffixs for these are:
232 // 0, 1, 5, 9, 2, 6, 10
233 // this suffix can then be calculated as follows:
234 // for a given argument Arg:
235 // Arg1x, Arg2x = 1 : Arg is sf
237 // 0: Arg is neither sf or df
238 // So this stub is the string for number Arg1x + Arg2x*4.
239 // However not all numbers between 0 and 10 are possible, we check anyway and
240 // assert if the impossible exists.
243 unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber
244 (ArgListTy &Args) const {
245 unsigned int resultNum = 0;
246 if (Args.size() >= 1) {
247 Type *t = Args[0].Ty;
248 if (t->isFloatTy()) {
251 else if (t->isDoubleTy()) {
256 if (Args.size() >=2) {
257 Type *t = Args[1].Ty;
258 if (t->isFloatTy()) {
261 else if (t->isDoubleTy()) {
270 // prefixs are attached to stub numbers depending on the return type .
271 // return type: float sf_
273 // single complex sc_
274 // double complext dc_
278 // The full name of a helper function is__mips16_call_stub +
279 // return type dependent prefix + stub number
282 // This is something that probably should be in a different source file and
283 // perhaps done differently but my main purpose is to not waste runtime
284 // on something that we can enumerate in the source. Another possibility is
285 // to have a python script to generate these mapping tables. This will do
286 // for now. There are a whole series of helper function mapping arrays, one
287 // for each return type class as outlined above. There there are 11 possible
288 // entries. Ones with 0 are ones which should never be selected
290 // All the arrays are similar except for ones which return neither
291 // sf, df, sc, dc, in which only care about ones which have sf or df as a
294 #define P_ "__mips16_call_stub_"
295 #define MAX_STUB_NUMBER 10
296 #define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
299 static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
303 static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
307 static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
311 static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
315 static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
321 const char* Mips16TargetLowering::
322 getMips16HelperFunction
323 (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
324 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
326 const unsigned int maxStubNum = 10;
327 assert(stubNum <= maxStubNum);
328 const bool validStubNum[maxStubNum+1] =
329 {true, true, true, false, false, true, true, false, false, true, true};
330 assert(validStubNum[stubNum]);
333 if (RetTy->isFloatTy()) {
334 result = sfMips16Helper[stubNum];
336 else if (RetTy ->isDoubleTy()) {
337 result = dfMips16Helper[stubNum];
339 else if (RetTy->isStructTy()) {
340 // check if it's complex
341 if (RetTy->getNumContainedTypes() == 2) {
342 if ((RetTy->getContainedType(0)->isFloatTy()) &&
343 (RetTy->getContainedType(1)->isFloatTy())) {
344 result = scMips16Helper[stubNum];
346 else if ((RetTy->getContainedType(0)->isDoubleTy()) &&
347 (RetTy->getContainedType(1)->isDoubleTy())) {
348 result = dcMips16Helper[stubNum];
351 llvm_unreachable("Uncovered condition");
355 llvm_unreachable("Uncovered condition");
363 result = vMips16Helper[stubNum];
369 void Mips16TargetLowering::
370 getOpndList(SmallVectorImpl<SDValue> &Ops,
371 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
372 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
373 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
374 SelectionDAG &DAG = CLI.DAG;
375 const char* Mips16HelperFunction = 0;
376 bool NeedMips16Helper = false;
378 if (getTargetMachine().Options.UseSoftFloat && Mips16HardFloat) {
380 // currently we don't have symbols tagged with the mips16 or mips32
381 // qualifier so we will assume that we don't know what kind it is.
382 // and generate the helper
384 bool LookupHelper = true;
385 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) {
386 if (NoHelperNeeded.find(S->getSymbol()) != NoHelperNeeded.end()) {
387 LookupHelper = false;
390 if (LookupHelper) Mips16HelperFunction =
391 getMips16HelperFunction(CLI.RetTy, CLI.Args, NeedMips16Helper);
395 SDValue JumpTarget = Callee;
397 // T9 should contain the address of the callee function if
398 // -reloction-model=pic or it is an indirect call.
399 if (IsPICCall || !GlobalOrExternal) {
400 unsigned V0Reg = Mips::V0;
401 if (NeedMips16Helper) {
402 RegsToPass.push_front(std::make_pair(V0Reg, Callee));
403 JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction, getPointerTy());
404 JumpTarget = getAddrGlobal(JumpTarget, DAG, MipsII::MO_GOT);
406 RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee));
409 Ops.push_back(JumpTarget);
411 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
412 InternalLinkage, CLI, Callee, Chain);
415 MachineBasicBlock *Mips16TargetLowering::
416 emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const {
417 if (DontExpandCondPseudos16)
419 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
420 DebugLoc DL = MI->getDebugLoc();
421 // To "insert" a SELECT_CC instruction, we actually have to insert the
422 // diamond control-flow pattern. The incoming instruction knows the
423 // destination vreg to set, the condition code register to branch on, the
424 // true/false values to select between, and a branch opcode to use.
425 const BasicBlock *LLVM_BB = BB->getBasicBlock();
426 MachineFunction::iterator It = BB;
433 // bNE r1, r0, copy1MBB
434 // fallthrough --> copy0MBB
435 MachineBasicBlock *thisMBB = BB;
436 MachineFunction *F = BB->getParent();
437 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
438 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
439 F->insert(It, copy0MBB);
440 F->insert(It, sinkMBB);
442 // Transfer the remainder of BB and its successor edges to sinkMBB.
443 sinkMBB->splice(sinkMBB->begin(), BB,
444 llvm::next(MachineBasicBlock::iterator(MI)),
446 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
448 // Next, add the true and fallthrough blocks as its successors.
449 BB->addSuccessor(copy0MBB);
450 BB->addSuccessor(sinkMBB);
452 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
457 // # fallthrough to sinkMBB
460 // Update machine-CFG edges
461 BB->addSuccessor(sinkMBB);
464 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
468 BuildMI(*BB, BB->begin(), DL,
469 TII->get(Mips::PHI), MI->getOperand(0).getReg())
470 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
471 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
473 MI->eraseFromParent(); // The pseudo instruction is gone now.
477 MachineBasicBlock *Mips16TargetLowering::emitSelT16
478 (unsigned Opc1, unsigned Opc2,
479 MachineInstr *MI, MachineBasicBlock *BB) const {
480 if (DontExpandCondPseudos16)
482 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
483 DebugLoc DL = MI->getDebugLoc();
484 // To "insert" a SELECT_CC instruction, we actually have to insert the
485 // diamond control-flow pattern. The incoming instruction knows the
486 // destination vreg to set, the condition code register to branch on, the
487 // true/false values to select between, and a branch opcode to use.
488 const BasicBlock *LLVM_BB = BB->getBasicBlock();
489 MachineFunction::iterator It = BB;
496 // bNE r1, r0, copy1MBB
497 // fallthrough --> copy0MBB
498 MachineBasicBlock *thisMBB = BB;
499 MachineFunction *F = BB->getParent();
500 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
501 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
502 F->insert(It, copy0MBB);
503 F->insert(It, sinkMBB);
505 // Transfer the remainder of BB and its successor edges to sinkMBB.
506 sinkMBB->splice(sinkMBB->begin(), BB,
507 llvm::next(MachineBasicBlock::iterator(MI)),
509 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
511 // Next, add the true and fallthrough blocks as its successors.
512 BB->addSuccessor(copy0MBB);
513 BB->addSuccessor(sinkMBB);
515 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
516 .addReg(MI->getOperand(4).getReg());
517 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
521 // # fallthrough to sinkMBB
524 // Update machine-CFG edges
525 BB->addSuccessor(sinkMBB);
528 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
532 BuildMI(*BB, BB->begin(), DL,
533 TII->get(Mips::PHI), MI->getOperand(0).getReg())
534 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
535 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
537 MI->eraseFromParent(); // The pseudo instruction is gone now.
542 MachineBasicBlock *Mips16TargetLowering::emitSeliT16
543 (unsigned Opc1, unsigned Opc2,
544 MachineInstr *MI, MachineBasicBlock *BB) const {
545 if (DontExpandCondPseudos16)
547 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
548 DebugLoc DL = MI->getDebugLoc();
549 // To "insert" a SELECT_CC instruction, we actually have to insert the
550 // diamond control-flow pattern. The incoming instruction knows the
551 // destination vreg to set, the condition code register to branch on, the
552 // true/false values to select between, and a branch opcode to use.
553 const BasicBlock *LLVM_BB = BB->getBasicBlock();
554 MachineFunction::iterator It = BB;
561 // bNE r1, r0, copy1MBB
562 // fallthrough --> copy0MBB
563 MachineBasicBlock *thisMBB = BB;
564 MachineFunction *F = BB->getParent();
565 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
566 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
567 F->insert(It, copy0MBB);
568 F->insert(It, sinkMBB);
570 // Transfer the remainder of BB and its successor edges to sinkMBB.
571 sinkMBB->splice(sinkMBB->begin(), BB,
572 llvm::next(MachineBasicBlock::iterator(MI)),
574 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
576 // Next, add the true and fallthrough blocks as its successors.
577 BB->addSuccessor(copy0MBB);
578 BB->addSuccessor(sinkMBB);
580 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
581 .addImm(MI->getOperand(4).getImm());
582 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
586 // # fallthrough to sinkMBB
589 // Update machine-CFG edges
590 BB->addSuccessor(sinkMBB);
593 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
597 BuildMI(*BB, BB->begin(), DL,
598 TII->get(Mips::PHI), MI->getOperand(0).getReg())
599 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
600 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
602 MI->eraseFromParent(); // The pseudo instruction is gone now.
608 *Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
610 MachineBasicBlock *BB) const {
611 if (DontExpandCondPseudos16)
613 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
614 unsigned regX = MI->getOperand(0).getReg();
615 unsigned regY = MI->getOperand(1).getReg();
616 MachineBasicBlock *target = MI->getOperand(2).getMBB();
617 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addReg(regY);
618 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
619 MI->eraseFromParent(); // The pseudo instruction is gone now.
623 MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins(
624 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc,
625 MachineInstr *MI, MachineBasicBlock *BB) const {
626 if (DontExpandCondPseudos16)
628 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
629 unsigned regX = MI->getOperand(0).getReg();
630 int64_t imm = MI->getOperand(1).getImm();
631 MachineBasicBlock *target = MI->getOperand(2).getMBB();
635 else if (isUInt<16>(imm))
638 llvm_unreachable("immediate field not usable");
639 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
640 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
641 MI->eraseFromParent(); // The pseudo instruction is gone now.
645 static unsigned Mips16WhichOp8uOr16simm
646 (unsigned shortOp, unsigned longOp, int64_t Imm) {
649 else if (isInt<16>(Imm))
652 llvm_unreachable("immediate field not usable");
655 MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRX16_ins(
657 MachineInstr *MI, MachineBasicBlock *BB) const {
658 if (DontExpandCondPseudos16)
660 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
661 unsigned CC = MI->getOperand(0).getReg();
662 unsigned regX = MI->getOperand(1).getReg();
663 unsigned regY = MI->getOperand(2).getReg();
664 BuildMI(*BB, MI, MI->getDebugLoc(),
665 TII->get(SltOpc)).addReg(regX).addReg(regY);
666 BuildMI(*BB, MI, MI->getDebugLoc(),
667 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
668 MI->eraseFromParent(); // The pseudo instruction is gone now.
672 MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRXI16_ins(
673 unsigned SltiOpc, unsigned SltiXOpc,
674 MachineInstr *MI, MachineBasicBlock *BB )const {
675 if (DontExpandCondPseudos16)
677 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
678 unsigned CC = MI->getOperand(0).getReg();
679 unsigned regX = MI->getOperand(1).getReg();
680 int64_t Imm = MI->getOperand(2).getImm();
681 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
682 BuildMI(*BB, MI, MI->getDebugLoc(),
683 TII->get(SltOpc)).addReg(regX).addImm(Imm);
684 BuildMI(*BB, MI, MI->getDebugLoc(),
685 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
686 MI->eraseFromParent(); // The pseudo instruction is gone now.