1 //===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips16.
12 //===----------------------------------------------------------------------===//
13 #include "Mips16ISelLowering.h"
14 #include "MCTargetDesc/MipsBaseInfo.h"
15 #include "MipsRegisterInfo.h"
16 #include "MipsTargetMachine.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Target/TargetInstrInfo.h"
25 #define DEBUG_TYPE "mips-lower"
27 static cl::opt<bool> DontExpandCondPseudos16(
28 "mips16-dont-expand-cond-pseudo",
30 cl::desc("Dont expand conditional move related "
31 "pseudos for Mips 16"),
35 struct Mips16Libcall {
36 RTLIB::Libcall Libcall;
39 bool operator<(const Mips16Libcall &RHS) const {
40 return std::strcmp(Name, RHS.Name) < 0;
44 struct Mips16IntrinsicHelperType{
48 bool operator<(const Mips16IntrinsicHelperType &RHS) const {
49 return std::strcmp(Name, RHS.Name) < 0;
51 bool operator==(const Mips16IntrinsicHelperType &RHS) const {
52 return std::strcmp(Name, RHS.Name) == 0;
57 // Libcalls for which no helper is generated. Sorted by name for binary search.
58 static const Mips16Libcall HardFloatLibCalls[] = {
59 { RTLIB::ADD_F64, "__mips16_adddf3" },
60 { RTLIB::ADD_F32, "__mips16_addsf3" },
61 { RTLIB::DIV_F64, "__mips16_divdf3" },
62 { RTLIB::DIV_F32, "__mips16_divsf3" },
63 { RTLIB::OEQ_F64, "__mips16_eqdf2" },
64 { RTLIB::OEQ_F32, "__mips16_eqsf2" },
65 { RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2" },
66 { RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi" },
67 { RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi" },
68 { RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf" },
69 { RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf" },
70 { RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf" },
71 { RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf" },
72 { RTLIB::OGE_F64, "__mips16_gedf2" },
73 { RTLIB::OGE_F32, "__mips16_gesf2" },
74 { RTLIB::OGT_F64, "__mips16_gtdf2" },
75 { RTLIB::OGT_F32, "__mips16_gtsf2" },
76 { RTLIB::OLE_F64, "__mips16_ledf2" },
77 { RTLIB::OLE_F32, "__mips16_lesf2" },
78 { RTLIB::OLT_F64, "__mips16_ltdf2" },
79 { RTLIB::OLT_F32, "__mips16_ltsf2" },
80 { RTLIB::MUL_F64, "__mips16_muldf3" },
81 { RTLIB::MUL_F32, "__mips16_mulsf3" },
82 { RTLIB::UNE_F64, "__mips16_nedf2" },
83 { RTLIB::UNE_F32, "__mips16_nesf2" },
84 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_dc" }, // No associated libcall.
85 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_df" }, // No associated libcall.
86 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sc" }, // No associated libcall.
87 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sf" }, // No associated libcall.
88 { RTLIB::SUB_F64, "__mips16_subdf3" },
89 { RTLIB::SUB_F32, "__mips16_subsf3" },
90 { RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2" },
91 { RTLIB::UO_F64, "__mips16_unorddf2" },
92 { RTLIB::UO_F32, "__mips16_unordsf2" }
95 static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = {
96 {"__fixunsdfsi", "__mips16_call_stub_2" },
97 {"ceil", "__mips16_call_stub_df_2"},
98 {"ceilf", "__mips16_call_stub_sf_1"},
99 {"copysign", "__mips16_call_stub_df_10"},
100 {"copysignf", "__mips16_call_stub_sf_5"},
101 {"cos", "__mips16_call_stub_df_2"},
102 {"cosf", "__mips16_call_stub_sf_1"},
103 {"exp2", "__mips16_call_stub_df_2"},
104 {"exp2f", "__mips16_call_stub_sf_1"},
105 {"floor", "__mips16_call_stub_df_2"},
106 {"floorf", "__mips16_call_stub_sf_1"},
107 {"log2", "__mips16_call_stub_df_2"},
108 {"log2f", "__mips16_call_stub_sf_1"},
109 {"nearbyint", "__mips16_call_stub_df_2"},
110 {"nearbyintf", "__mips16_call_stub_sf_1"},
111 {"rint", "__mips16_call_stub_df_2"},
112 {"rintf", "__mips16_call_stub_sf_1"},
113 {"sin", "__mips16_call_stub_df_2"},
114 {"sinf", "__mips16_call_stub_sf_1"},
115 {"sqrt", "__mips16_call_stub_df_2"},
116 {"sqrtf", "__mips16_call_stub_sf_1"},
117 {"trunc", "__mips16_call_stub_df_2"},
118 {"truncf", "__mips16_call_stub_sf_1"},
121 Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM,
122 const MipsSubtarget &STI)
123 : MipsTargetLowering(TM, STI) {
125 // Set up the register classes
126 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
128 if (!TM.Options.UseSoftFloat)
129 setMips16HardFloatLibCalls();
131 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
132 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
133 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
134 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
135 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
136 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
137 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
138 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
139 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
140 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
141 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
142 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
143 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
145 setOperationAction(ISD::ROTR, MVT::i32, Expand);
146 setOperationAction(ISD::ROTR, MVT::i64, Expand);
147 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
148 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
150 computeRegisterProperties();
153 const MipsTargetLowering *
154 llvm::createMips16TargetLowering(MipsTargetMachine &TM,
155 const MipsSubtarget &STI) {
156 return new Mips16TargetLowering(TM, STI);
160 Mips16TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
168 Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
169 MachineBasicBlock *BB) const {
170 switch (MI->getOpcode()) {
172 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
174 return emitSel16(Mips::BeqzRxImm16, MI, BB);
176 return emitSel16(Mips::BnezRxImm16, MI, BB);
177 case Mips::SelTBteqZCmpi:
178 return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB);
179 case Mips::SelTBteqZSlti:
180 return emitSeliT16(Mips::Bteqz16, Mips::SltiRxImmX16, MI, BB);
181 case Mips::SelTBteqZSltiu:
182 return emitSeliT16(Mips::Bteqz16, Mips::SltiuRxImmX16, MI, BB);
183 case Mips::SelTBtneZCmpi:
184 return emitSeliT16(Mips::Btnez16, Mips::CmpiRxImmX16, MI, BB);
185 case Mips::SelTBtneZSlti:
186 return emitSeliT16(Mips::Btnez16, Mips::SltiRxImmX16, MI, BB);
187 case Mips::SelTBtneZSltiu:
188 return emitSeliT16(Mips::Btnez16, Mips::SltiuRxImmX16, MI, BB);
189 case Mips::SelTBteqZCmp:
190 return emitSelT16(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
191 case Mips::SelTBteqZSlt:
192 return emitSelT16(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
193 case Mips::SelTBteqZSltu:
194 return emitSelT16(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
195 case Mips::SelTBtneZCmp:
196 return emitSelT16(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
197 case Mips::SelTBtneZSlt:
198 return emitSelT16(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
199 case Mips::SelTBtneZSltu:
200 return emitSelT16(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
201 case Mips::BteqzT8CmpX16:
202 return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
203 case Mips::BteqzT8SltX16:
204 return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
205 case Mips::BteqzT8SltuX16:
206 // TBD: figure out a way to get this or remove the instruction
208 return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
209 case Mips::BtnezT8CmpX16:
210 return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
211 case Mips::BtnezT8SltX16:
212 return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
213 case Mips::BtnezT8SltuX16:
214 // TBD: figure out a way to get this or remove the instruction
216 return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
217 case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins(
218 Mips::Bteqz16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
219 case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins(
220 Mips::Bteqz16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
221 case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins(
222 Mips::Bteqz16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
223 case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins(
224 Mips::Btnez16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
225 case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins(
226 Mips::Btnez16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
227 case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins(
228 Mips::Btnez16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
230 case Mips::SltCCRxRy16:
231 return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
233 case Mips::SltiCCRxImmX16:
234 return emitFEXT_CCRXI16_ins
235 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
236 case Mips::SltiuCCRxImmX16:
237 return emitFEXT_CCRXI16_ins
238 (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
239 case Mips::SltuCCRxRy16:
240 return emitFEXT_CCRX16_ins
241 (Mips::SltuRxRy16, MI, BB);
245 bool Mips16TargetLowering::
246 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
247 unsigned NextStackOffset,
248 const MipsFunctionInfo& FI) const {
249 // No tail call optimization for mips16.
253 void Mips16TargetLowering::setMips16HardFloatLibCalls() {
254 for (unsigned I = 0; I != array_lengthof(HardFloatLibCalls); ++I) {
255 assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) &&
256 "Array not sorted!");
257 if (HardFloatLibCalls[I].Libcall != RTLIB::UNKNOWN_LIBCALL)
258 setLibcallName(HardFloatLibCalls[I].Libcall, HardFloatLibCalls[I].Name);
261 setLibcallName(RTLIB::O_F64, "__mips16_unorddf2");
262 setLibcallName(RTLIB::O_F32, "__mips16_unordsf2");
266 // The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
267 // cleaner way to do all of this but it will have to wait until the traditional
268 // gcc mechanism is completed.
270 // For Pic, in order for Mips16 code to call Mips32 code which according the abi
271 // have either arguments or returned values placed in floating point registers,
272 // we use a set of helper functions. (This includes functions which return type
273 // complex which on Mips are returned in a pair of floating point registers).
275 // This is an encoding that we inherited from gcc.
276 // In Mips traditional O32, N32 ABI, floating point numbers are passed in
277 // floating point argument registers 1,2 only when the first and optionally
278 // the second arguments are float (sf) or double (df).
279 // For Mips16 we are only concerned with the situations where floating point
280 // arguments are being passed in floating point registers by the ABI, because
281 // Mips16 mode code cannot execute floating point instructions to load those
282 // values and hence helper functions are needed.
283 // The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
284 // the helper function suffixs for these are:
285 // 0, 1, 5, 9, 2, 6, 10
286 // this suffix can then be calculated as follows:
287 // for a given argument Arg:
288 // Arg1x, Arg2x = 1 : Arg is sf
290 // 0: Arg is neither sf or df
291 // So this stub is the string for number Arg1x + Arg2x*4.
292 // However not all numbers between 0 and 10 are possible, we check anyway and
293 // assert if the impossible exists.
296 unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber
297 (ArgListTy &Args) const {
298 unsigned int resultNum = 0;
299 if (Args.size() >= 1) {
300 Type *t = Args[0].Ty;
301 if (t->isFloatTy()) {
304 else if (t->isDoubleTy()) {
309 if (Args.size() >=2) {
310 Type *t = Args[1].Ty;
311 if (t->isFloatTy()) {
314 else if (t->isDoubleTy()) {
323 // prefixs are attached to stub numbers depending on the return type .
324 // return type: float sf_
326 // single complex sc_
327 // double complext dc_
331 // The full name of a helper function is__mips16_call_stub +
332 // return type dependent prefix + stub number
335 // This is something that probably should be in a different source file and
336 // perhaps done differently but my main purpose is to not waste runtime
337 // on something that we can enumerate in the source. Another possibility is
338 // to have a python script to generate these mapping tables. This will do
339 // for now. There are a whole series of helper function mapping arrays, one
340 // for each return type class as outlined above. There there are 11 possible
341 // entries. Ones with 0 are ones which should never be selected
343 // All the arrays are similar except for ones which return neither
344 // sf, df, sc, dc, in which only care about ones which have sf or df as a
347 #define P_ "__mips16_call_stub_"
348 #define MAX_STUB_NUMBER 10
349 #define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
352 static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
356 static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
360 static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
364 static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
368 static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
374 const char* Mips16TargetLowering::
375 getMips16HelperFunction
376 (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
377 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
379 const unsigned int maxStubNum = 10;
380 assert(stubNum <= maxStubNum);
381 const bool validStubNum[maxStubNum+1] =
382 {true, true, true, false, false, true, true, false, false, true, true};
383 assert(validStubNum[stubNum]);
386 if (RetTy->isFloatTy()) {
387 result = sfMips16Helper[stubNum];
389 else if (RetTy ->isDoubleTy()) {
390 result = dfMips16Helper[stubNum];
392 else if (RetTy->isStructTy()) {
393 // check if it's complex
394 if (RetTy->getNumContainedTypes() == 2) {
395 if ((RetTy->getContainedType(0)->isFloatTy()) &&
396 (RetTy->getContainedType(1)->isFloatTy())) {
397 result = scMips16Helper[stubNum];
399 else if ((RetTy->getContainedType(0)->isDoubleTy()) &&
400 (RetTy->getContainedType(1)->isDoubleTy())) {
401 result = dcMips16Helper[stubNum];
404 llvm_unreachable("Uncovered condition");
408 llvm_unreachable("Uncovered condition");
416 result = vMips16Helper[stubNum];
422 void Mips16TargetLowering::
423 getOpndList(SmallVectorImpl<SDValue> &Ops,
424 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
425 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
426 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
427 SelectionDAG &DAG = CLI.DAG;
428 MachineFunction &MF = DAG.getMachineFunction();
429 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
430 const char* Mips16HelperFunction = nullptr;
431 bool NeedMips16Helper = false;
433 if (Subtarget.inMips16HardFloat()) {
435 // currently we don't have symbols tagged with the mips16 or mips32
436 // qualifier so we will assume that we don't know what kind it is.
437 // and generate the helper
439 bool LookupHelper = true;
440 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) {
441 Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, S->getSymbol() };
443 if (std::binary_search(std::begin(HardFloatLibCalls),
444 std::end(HardFloatLibCalls), Find))
445 LookupHelper = false;
447 const char *Symbol = S->getSymbol();
448 Mips16IntrinsicHelperType IntrinsicFind = { Symbol, "" };
449 const Mips16HardFloatInfo::FuncSignature *Signature =
450 Mips16HardFloatInfo::findFuncSignature(Symbol);
451 if (!IsPICCall && (Signature && (FuncInfo->StubsNeeded.find(Symbol) ==
452 FuncInfo->StubsNeeded.end()))) {
453 FuncInfo->StubsNeeded[Symbol] = Signature;
455 // S2 is normally saved if the stub is for a function which
456 // returns a float or double value and is not otherwise. This is
457 // because more work is required after the function the stub
458 // is calling completes, and so the stub cannot directly return
459 // and the stub has no stack space to store the return address so
460 // S2 is used for that purpose.
461 // In order to take advantage of not saving S2, we need to also
462 // optimize the call in the stub and this requires some further
463 // functionality in MipsAsmPrinter which we don't have yet.
464 // So for now we always save S2. The optimization will be done
465 // in a follow-on patch.
467 if (1 || (Signature->RetSig != Mips16HardFloatInfo::NoFPRet))
468 FuncInfo->setSaveS2();
470 // one more look at list of intrinsics
471 const Mips16IntrinsicHelperType *Helper =
472 std::lower_bound(std::begin(Mips16IntrinsicHelper),
473 std::end(Mips16IntrinsicHelper), IntrinsicFind);
474 if (Helper != std::end(Mips16IntrinsicHelper) &&
475 *Helper == IntrinsicFind) {
476 Mips16HelperFunction = Helper->Helper;
477 NeedMips16Helper = true;
478 LookupHelper = false;
482 } else if (GlobalAddressSDNode *G =
483 dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
484 Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL,
485 G->getGlobal()->getName().data() };
487 if (std::binary_search(std::begin(HardFloatLibCalls),
488 std::end(HardFloatLibCalls), Find))
489 LookupHelper = false;
492 Mips16HelperFunction =
493 getMips16HelperFunction(CLI.RetTy, CLI.getArgs(), NeedMips16Helper);
496 SDValue JumpTarget = Callee;
498 // T9 should contain the address of the callee function if
499 // -reloction-model=pic or it is an indirect call.
500 if (IsPICCall || !GlobalOrExternal) {
501 unsigned V0Reg = Mips::V0;
502 if (NeedMips16Helper) {
503 RegsToPass.push_front(std::make_pair(V0Reg, Callee));
504 JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction, getPointerTy());
505 ExternalSymbolSDNode *S = cast<ExternalSymbolSDNode>(JumpTarget);
506 JumpTarget = getAddrGlobal(S, JumpTarget.getValueType(), DAG,
507 MipsII::MO_GOT, Chain,
508 FuncInfo->callPtrInfo(S->getSymbol()));
510 RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee));
513 Ops.push_back(JumpTarget);
515 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
516 InternalLinkage, CLI, Callee, Chain);
519 MachineBasicBlock *Mips16TargetLowering::
520 emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const {
521 if (DontExpandCondPseudos16)
523 const TargetInstrInfo *TII =
524 getTargetMachine().getSubtargetImpl()->getInstrInfo();
525 DebugLoc DL = MI->getDebugLoc();
526 // To "insert" a SELECT_CC instruction, we actually have to insert the
527 // diamond control-flow pattern. The incoming instruction knows the
528 // destination vreg to set, the condition code register to branch on, the
529 // true/false values to select between, and a branch opcode to use.
530 const BasicBlock *LLVM_BB = BB->getBasicBlock();
531 MachineFunction::iterator It = BB;
538 // bNE r1, r0, copy1MBB
539 // fallthrough --> copy0MBB
540 MachineBasicBlock *thisMBB = BB;
541 MachineFunction *F = BB->getParent();
542 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
543 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
544 F->insert(It, copy0MBB);
545 F->insert(It, sinkMBB);
547 // Transfer the remainder of BB and its successor edges to sinkMBB.
548 sinkMBB->splice(sinkMBB->begin(), BB,
549 std::next(MachineBasicBlock::iterator(MI)), BB->end());
550 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
552 // Next, add the true and fallthrough blocks as its successors.
553 BB->addSuccessor(copy0MBB);
554 BB->addSuccessor(sinkMBB);
556 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
561 // # fallthrough to sinkMBB
564 // Update machine-CFG edges
565 BB->addSuccessor(sinkMBB);
568 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
572 BuildMI(*BB, BB->begin(), DL,
573 TII->get(Mips::PHI), MI->getOperand(0).getReg())
574 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
575 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
577 MI->eraseFromParent(); // The pseudo instruction is gone now.
581 MachineBasicBlock *Mips16TargetLowering::emitSelT16
582 (unsigned Opc1, unsigned Opc2,
583 MachineInstr *MI, MachineBasicBlock *BB) const {
584 if (DontExpandCondPseudos16)
586 const TargetInstrInfo *TII =
587 getTargetMachine().getSubtargetImpl()->getInstrInfo();
588 DebugLoc DL = MI->getDebugLoc();
589 // To "insert" a SELECT_CC instruction, we actually have to insert the
590 // diamond control-flow pattern. The incoming instruction knows the
591 // destination vreg to set, the condition code register to branch on, the
592 // true/false values to select between, and a branch opcode to use.
593 const BasicBlock *LLVM_BB = BB->getBasicBlock();
594 MachineFunction::iterator It = BB;
601 // bNE r1, r0, copy1MBB
602 // fallthrough --> copy0MBB
603 MachineBasicBlock *thisMBB = BB;
604 MachineFunction *F = BB->getParent();
605 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
606 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
607 F->insert(It, copy0MBB);
608 F->insert(It, sinkMBB);
610 // Transfer the remainder of BB and its successor edges to sinkMBB.
611 sinkMBB->splice(sinkMBB->begin(), BB,
612 std::next(MachineBasicBlock::iterator(MI)), BB->end());
613 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
615 // Next, add the true and fallthrough blocks as its successors.
616 BB->addSuccessor(copy0MBB);
617 BB->addSuccessor(sinkMBB);
619 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
620 .addReg(MI->getOperand(4).getReg());
621 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
625 // # fallthrough to sinkMBB
628 // Update machine-CFG edges
629 BB->addSuccessor(sinkMBB);
632 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
636 BuildMI(*BB, BB->begin(), DL,
637 TII->get(Mips::PHI), MI->getOperand(0).getReg())
638 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
639 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
641 MI->eraseFromParent(); // The pseudo instruction is gone now.
646 MachineBasicBlock *Mips16TargetLowering::emitSeliT16
647 (unsigned Opc1, unsigned Opc2,
648 MachineInstr *MI, MachineBasicBlock *BB) const {
649 if (DontExpandCondPseudos16)
651 const TargetInstrInfo *TII =
652 getTargetMachine().getSubtargetImpl()->getInstrInfo();
653 DebugLoc DL = MI->getDebugLoc();
654 // To "insert" a SELECT_CC instruction, we actually have to insert the
655 // diamond control-flow pattern. The incoming instruction knows the
656 // destination vreg to set, the condition code register to branch on, the
657 // true/false values to select between, and a branch opcode to use.
658 const BasicBlock *LLVM_BB = BB->getBasicBlock();
659 MachineFunction::iterator It = BB;
666 // bNE r1, r0, copy1MBB
667 // fallthrough --> copy0MBB
668 MachineBasicBlock *thisMBB = BB;
669 MachineFunction *F = BB->getParent();
670 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
671 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
672 F->insert(It, copy0MBB);
673 F->insert(It, sinkMBB);
675 // Transfer the remainder of BB and its successor edges to sinkMBB.
676 sinkMBB->splice(sinkMBB->begin(), BB,
677 std::next(MachineBasicBlock::iterator(MI)), BB->end());
678 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
680 // Next, add the true and fallthrough blocks as its successors.
681 BB->addSuccessor(copy0MBB);
682 BB->addSuccessor(sinkMBB);
684 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
685 .addImm(MI->getOperand(4).getImm());
686 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
690 // # fallthrough to sinkMBB
693 // Update machine-CFG edges
694 BB->addSuccessor(sinkMBB);
697 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
701 BuildMI(*BB, BB->begin(), DL,
702 TII->get(Mips::PHI), MI->getOperand(0).getReg())
703 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
704 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
706 MI->eraseFromParent(); // The pseudo instruction is gone now.
712 *Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
714 MachineBasicBlock *BB) const {
715 if (DontExpandCondPseudos16)
717 const TargetInstrInfo *TII =
718 getTargetMachine().getSubtargetImpl()->getInstrInfo();
719 unsigned regX = MI->getOperand(0).getReg();
720 unsigned regY = MI->getOperand(1).getReg();
721 MachineBasicBlock *target = MI->getOperand(2).getMBB();
722 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX)
724 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
725 MI->eraseFromParent(); // The pseudo instruction is gone now.
729 MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins(
730 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned,
731 MachineInstr *MI, MachineBasicBlock *BB) const {
732 if (DontExpandCondPseudos16)
734 const TargetInstrInfo *TII =
735 getTargetMachine().getSubtargetImpl()->getInstrInfo();
736 unsigned regX = MI->getOperand(0).getReg();
737 int64_t imm = MI->getOperand(1).getImm();
738 MachineBasicBlock *target = MI->getOperand(2).getMBB();
742 else if ((!ImmSigned && isUInt<16>(imm)) ||
743 (ImmSigned && isInt<16>(imm)))
746 llvm_unreachable("immediate field not usable");
747 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX)
749 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
750 MI->eraseFromParent(); // The pseudo instruction is gone now.
754 static unsigned Mips16WhichOp8uOr16simm
755 (unsigned shortOp, unsigned longOp, int64_t Imm) {
758 else if (isInt<16>(Imm))
761 llvm_unreachable("immediate field not usable");
764 MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRX16_ins(
766 MachineInstr *MI, MachineBasicBlock *BB) const {
767 if (DontExpandCondPseudos16)
769 const TargetInstrInfo *TII =
770 getTargetMachine().getSubtargetImpl()->getInstrInfo();
771 unsigned CC = MI->getOperand(0).getReg();
772 unsigned regX = MI->getOperand(1).getReg();
773 unsigned regY = MI->getOperand(2).getReg();
774 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(SltOpc)).addReg(regX).addReg(
776 BuildMI(*BB, MI, MI->getDebugLoc(),
777 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
778 MI->eraseFromParent(); // The pseudo instruction is gone now.
782 MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRXI16_ins(
783 unsigned SltiOpc, unsigned SltiXOpc,
784 MachineInstr *MI, MachineBasicBlock *BB )const {
785 if (DontExpandCondPseudos16)
787 const TargetInstrInfo *TII =
788 getTargetMachine().getSubtargetImpl()->getInstrInfo();
789 unsigned CC = MI->getOperand(0).getReg();
790 unsigned regX = MI->getOperand(1).getReg();
791 int64_t Imm = MI->getOperand(2).getImm();
792 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
793 BuildMI(*BB, MI, MI->getDebugLoc(),
794 TII->get(SltOpc)).addReg(regX).addImm(Imm);
795 BuildMI(*BB, MI, MI->getDebugLoc(),
796 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
797 MI->eraseFromParent(); // The pseudo instruction is gone now.