1 //===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Subclass of MipsTargetLowering specialized for mips16.
12 //===----------------------------------------------------------------------===//
13 #define DEBUG_TYPE "mips-lower"
14 #include "Mips16ISelLowering.h"
15 #include "MipsRegisterInfo.h"
16 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Target/TargetInstrInfo.h"
25 Mips16HardFloat("mips16-hard-float", cl::NotHidden,
26 cl::desc("MIPS: mips16 hard float enable."),
29 static cl::opt<bool> DontExpandCondPseudos16(
30 "mips16-dont-expand-cond-pseudo",
32 cl::desc("Dont expand conditional move related "
33 "pseudos for Mips 16"),
37 std::set<const char*, MipsTargetLowering::LTStr> NoHelperNeeded;
40 Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM)
41 : MipsTargetLowering(TM) {
43 // set up as if mips32 and then revert so we can test the mechanism
45 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
46 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
47 computeRegisterProperties();
48 clearRegisterClasses();
50 // Set up the register classes
51 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
54 setMips16HardFloatLibCalls();
56 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
57 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
58 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
59 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
60 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
61 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
62 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
63 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
64 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
65 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
66 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
67 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
68 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
70 computeRegisterProperties();
73 const MipsTargetLowering *
74 llvm::createMips16TargetLowering(MipsTargetMachine &TM) {
75 return new Mips16TargetLowering(TM);
79 Mips16TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
84 Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
85 MachineBasicBlock *BB) const {
86 switch (MI->getOpcode()) {
88 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
90 return emitSel16(Mips::BeqzRxImm16, MI, BB);
92 return emitSel16(Mips::BnezRxImm16, MI, BB);
93 case Mips::SelTBteqZCmpi:
94 return emitSeliT16(Mips::BteqzX16, Mips::CmpiRxImmX16, MI, BB);
95 case Mips::SelTBteqZSlti:
96 return emitSeliT16(Mips::BteqzX16, Mips::SltiRxImmX16, MI, BB);
97 case Mips::SelTBteqZSltiu:
98 return emitSeliT16(Mips::BteqzX16, Mips::SltiuRxImmX16, MI, BB);
99 case Mips::SelTBtneZCmpi:
100 return emitSeliT16(Mips::BtnezX16, Mips::CmpiRxImmX16, MI, BB);
101 case Mips::SelTBtneZSlti:
102 return emitSeliT16(Mips::BtnezX16, Mips::SltiRxImmX16, MI, BB);
103 case Mips::SelTBtneZSltiu:
104 return emitSeliT16(Mips::BtnezX16, Mips::SltiuRxImmX16, MI, BB);
105 case Mips::SelTBteqZCmp:
106 return emitSelT16(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
107 case Mips::SelTBteqZSlt:
108 return emitSelT16(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
109 case Mips::SelTBteqZSltu:
110 return emitSelT16(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
111 case Mips::SelTBtneZCmp:
112 return emitSelT16(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
113 case Mips::SelTBtneZSlt:
114 return emitSelT16(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
115 case Mips::SelTBtneZSltu:
116 return emitSelT16(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
117 case Mips::BteqzT8CmpX16:
118 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
119 case Mips::BteqzT8SltX16:
120 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
121 case Mips::BteqzT8SltuX16:
122 // TBD: figure out a way to get this or remove the instruction
124 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
125 case Mips::BtnezT8CmpX16:
126 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
127 case Mips::BtnezT8SltX16:
128 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
129 case Mips::BtnezT8SltuX16:
130 // TBD: figure out a way to get this or remove the instruction
132 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
133 case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins(
134 Mips::BteqzX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, MI, BB);
135 case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins(
136 Mips::BteqzX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
137 case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins(
138 Mips::BteqzX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
139 case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins(
140 Mips::BtnezX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, MI, BB);
141 case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins(
142 Mips::BtnezX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
143 case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins(
144 Mips::BtnezX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
146 case Mips::SltCCRxRy16:
147 return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
149 case Mips::SltiCCRxImmX16:
150 return emitFEXT_CCRXI16_ins
151 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
152 case Mips::SltiuCCRxImmX16:
153 return emitFEXT_CCRXI16_ins
154 (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
155 case Mips::SltuCCRxRy16:
156 return emitFEXT_CCRX16_ins
157 (Mips::SltuRxRy16, MI, BB);
161 bool Mips16TargetLowering::
162 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
163 unsigned NextStackOffset,
164 const MipsFunctionInfo& FI) const {
165 // No tail call optimization for mips16.
169 void Mips16TargetLowering::setMips16LibcallName
170 (RTLIB::Libcall L, const char *Name) {
171 setLibcallName(L, Name);
172 NoHelperNeeded.insert(Name);
175 void Mips16TargetLowering::setMips16HardFloatLibCalls() {
176 setMips16LibcallName(RTLIB::ADD_F32, "__mips16_addsf3");
177 setMips16LibcallName(RTLIB::ADD_F64, "__mips16_adddf3");
178 setMips16LibcallName(RTLIB::SUB_F32, "__mips16_subsf3");
179 setMips16LibcallName(RTLIB::SUB_F64, "__mips16_subdf3");
180 setMips16LibcallName(RTLIB::MUL_F32, "__mips16_mulsf3");
181 setMips16LibcallName(RTLIB::MUL_F64, "__mips16_muldf3");
182 setMips16LibcallName(RTLIB::DIV_F32, "__mips16_divsf3");
183 setMips16LibcallName(RTLIB::DIV_F64, "__mips16_divdf3");
184 setMips16LibcallName(RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2");
185 setMips16LibcallName(RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2");
186 setMips16LibcallName(RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi");
187 setMips16LibcallName(RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi");
188 setMips16LibcallName(RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf");
189 setMips16LibcallName(RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf");
190 setMips16LibcallName(RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf");
191 setMips16LibcallName(RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf");
192 setMips16LibcallName(RTLIB::OEQ_F32, "__mips16_eqsf2");
193 setMips16LibcallName(RTLIB::OEQ_F64, "__mips16_eqdf2");
194 setMips16LibcallName(RTLIB::UNE_F32, "__mips16_nesf2");
195 setMips16LibcallName(RTLIB::UNE_F64, "__mips16_nedf2");
196 setMips16LibcallName(RTLIB::OGE_F32, "__mips16_gesf2");
197 setMips16LibcallName(RTLIB::OGE_F64, "__mips16_gedf2");
198 setMips16LibcallName(RTLIB::OLT_F32, "__mips16_ltsf2");
199 setMips16LibcallName(RTLIB::OLT_F64, "__mips16_ltdf2");
200 setMips16LibcallName(RTLIB::OLE_F32, "__mips16_lesf2");
201 setMips16LibcallName(RTLIB::OLE_F64, "__mips16_ledf2");
202 setMips16LibcallName(RTLIB::OGT_F32, "__mips16_gtsf2");
203 setMips16LibcallName(RTLIB::OGT_F64, "__mips16_gtdf2");
204 setMips16LibcallName(RTLIB::UO_F32, "__mips16_unordsf2");
205 setMips16LibcallName(RTLIB::UO_F64, "__mips16_unorddf2");
206 setMips16LibcallName(RTLIB::O_F32, "__mips16_unordsf2");
207 setMips16LibcallName(RTLIB::O_F64, "__mips16_unorddf2");
212 // The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
213 // cleaner way to do all of this but it will have to wait until the traditional
214 // gcc mechanism is completed.
216 // For Pic, in order for Mips16 code to call Mips32 code which according the abi
217 // have either arguments or returned values placed in floating point registers,
218 // we use a set of helper functions. (This includes functions which return type
219 // complex which on Mips are returned in a pair of floating point registers).
221 // This is an encoding that we inherited from gcc.
222 // In Mips traditional O32, N32 ABI, floating point numbers are passed in
223 // floating point argument registers 1,2 only when the first and optionally
224 // the second arguments are float (sf) or double (df).
225 // For Mips16 we are only concerned with the situations where floating point
226 // arguments are being passed in floating point registers by the ABI, because
227 // Mips16 mode code cannot execute floating point instructions to load those
228 // values and hence helper functions are needed.
229 // The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
230 // the helper function suffixs for these are:
231 // 0, 1, 5, 9, 2, 6, 10
232 // this suffix can then be calculated as follows:
233 // for a given argument Arg:
234 // Arg1x, Arg2x = 1 : Arg is sf
236 // 0: Arg is neither sf or df
237 // So this stub is the string for number Arg1x + Arg2x*4.
238 // However not all numbers between 0 and 10 are possible, we check anyway and
239 // assert if the impossible exists.
242 unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber
243 (ArgListTy &Args) const {
244 unsigned int resultNum = 0;
245 if (Args.size() >= 1) {
246 Type *t = Args[0].Ty;
247 if (t->isFloatTy()) {
250 else if (t->isDoubleTy()) {
255 if (Args.size() >=2) {
256 Type *t = Args[1].Ty;
257 if (t->isFloatTy()) {
260 else if (t->isDoubleTy()) {
269 // prefixs are attached to stub numbers depending on the return type .
270 // return type: float sf_
272 // single complex sc_
273 // double complext dc_
277 // The full name of a helper function is__mips16_call_stub +
278 // return type dependent prefix + stub number
281 // This is something that probably should be in a different source file and
282 // perhaps done differently but my main purpose is to not waste runtime
283 // on something that we can enumerate in the source. Another possibility is
284 // to have a python script to generate these mapping tables. This will do
285 // for now. There are a whole series of helper function mapping arrays, one
286 // for each return type class as outlined above. There there are 11 possible
287 // entries. Ones with 0 are ones which should never be selected
289 // All the arrays are similar except for ones which return neither
290 // sf, df, sc, dc, in which only care about ones which have sf or df as a
293 #define P_ "__mips16_call_stub_"
294 #define MAX_STUB_NUMBER 10
295 #define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
298 static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
302 static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
306 static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
310 static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
314 static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
320 const char* Mips16TargetLowering::
321 getMips16HelperFunction
322 (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
323 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
325 const unsigned int maxStubNum = 10;
326 assert(stubNum <= maxStubNum);
327 const bool validStubNum[maxStubNum+1] =
328 {true, true, true, false, false, true, true, false, false, true, true};
329 assert(validStubNum[stubNum]);
332 if (RetTy->isFloatTy()) {
333 result = sfMips16Helper[stubNum];
335 else if (RetTy ->isDoubleTy()) {
336 result = dfMips16Helper[stubNum];
338 else if (RetTy->isStructTy()) {
339 // check if it's complex
340 if (RetTy->getNumContainedTypes() == 2) {
341 if ((RetTy->getContainedType(0)->isFloatTy()) &&
342 (RetTy->getContainedType(1)->isFloatTy())) {
343 result = scMips16Helper[stubNum];
345 else if ((RetTy->getContainedType(0)->isDoubleTy()) &&
346 (RetTy->getContainedType(1)->isDoubleTy())) {
347 result = dcMips16Helper[stubNum];
350 llvm_unreachable("Uncovered condition");
354 llvm_unreachable("Uncovered condition");
362 result = vMips16Helper[stubNum];
368 void Mips16TargetLowering::
369 getOpndList(SmallVectorImpl<SDValue> &Ops,
370 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
371 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
372 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
373 SelectionDAG &DAG = CLI.DAG;
374 const char* Mips16HelperFunction = 0;
375 bool NeedMips16Helper = false;
377 if (getTargetMachine().Options.UseSoftFloat && Mips16HardFloat) {
379 // currently we don't have symbols tagged with the mips16 or mips32
380 // qualifier so we will assume that we don't know what kind it is.
381 // and generate the helper
383 bool LookupHelper = true;
384 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) {
385 if (NoHelperNeeded.find(S->getSymbol()) != NoHelperNeeded.end()) {
386 LookupHelper = false;
389 if (LookupHelper) Mips16HelperFunction =
390 getMips16HelperFunction(CLI.RetTy, CLI.Args, NeedMips16Helper);
394 SDValue JumpTarget = Callee;
396 // T9 should contain the address of the callee function if
397 // -reloction-model=pic or it is an indirect call.
398 if (IsPICCall || !GlobalOrExternal) {
399 unsigned V0Reg = Mips::V0;
400 if (NeedMips16Helper) {
401 RegsToPass.push_front(std::make_pair(V0Reg, Callee));
402 JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction, getPointerTy());
403 JumpTarget = getAddrGlobal(JumpTarget, DAG, MipsII::MO_GOT);
405 RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee));
408 Ops.push_back(JumpTarget);
410 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
411 InternalLinkage, CLI, Callee, Chain);
414 MachineBasicBlock *Mips16TargetLowering::
415 emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const {
416 if (DontExpandCondPseudos16)
418 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
419 DebugLoc DL = MI->getDebugLoc();
420 // To "insert" a SELECT_CC instruction, we actually have to insert the
421 // diamond control-flow pattern. The incoming instruction knows the
422 // destination vreg to set, the condition code register to branch on, the
423 // true/false values to select between, and a branch opcode to use.
424 const BasicBlock *LLVM_BB = BB->getBasicBlock();
425 MachineFunction::iterator It = BB;
432 // bNE r1, r0, copy1MBB
433 // fallthrough --> copy0MBB
434 MachineBasicBlock *thisMBB = BB;
435 MachineFunction *F = BB->getParent();
436 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
437 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
438 F->insert(It, copy0MBB);
439 F->insert(It, sinkMBB);
441 // Transfer the remainder of BB and its successor edges to sinkMBB.
442 sinkMBB->splice(sinkMBB->begin(), BB,
443 llvm::next(MachineBasicBlock::iterator(MI)),
445 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
447 // Next, add the true and fallthrough blocks as its successors.
448 BB->addSuccessor(copy0MBB);
449 BB->addSuccessor(sinkMBB);
451 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
456 // # fallthrough to sinkMBB
459 // Update machine-CFG edges
460 BB->addSuccessor(sinkMBB);
463 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
467 BuildMI(*BB, BB->begin(), DL,
468 TII->get(Mips::PHI), MI->getOperand(0).getReg())
469 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
470 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
472 MI->eraseFromParent(); // The pseudo instruction is gone now.
476 MachineBasicBlock *Mips16TargetLowering::emitSelT16
477 (unsigned Opc1, unsigned Opc2,
478 MachineInstr *MI, MachineBasicBlock *BB) const {
479 if (DontExpandCondPseudos16)
481 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
482 DebugLoc DL = MI->getDebugLoc();
483 // To "insert" a SELECT_CC instruction, we actually have to insert the
484 // diamond control-flow pattern. The incoming instruction knows the
485 // destination vreg to set, the condition code register to branch on, the
486 // true/false values to select between, and a branch opcode to use.
487 const BasicBlock *LLVM_BB = BB->getBasicBlock();
488 MachineFunction::iterator It = BB;
495 // bNE r1, r0, copy1MBB
496 // fallthrough --> copy0MBB
497 MachineBasicBlock *thisMBB = BB;
498 MachineFunction *F = BB->getParent();
499 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
500 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
501 F->insert(It, copy0MBB);
502 F->insert(It, sinkMBB);
504 // Transfer the remainder of BB and its successor edges to sinkMBB.
505 sinkMBB->splice(sinkMBB->begin(), BB,
506 llvm::next(MachineBasicBlock::iterator(MI)),
508 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
510 // Next, add the true and fallthrough blocks as its successors.
511 BB->addSuccessor(copy0MBB);
512 BB->addSuccessor(sinkMBB);
514 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
515 .addReg(MI->getOperand(4).getReg());
516 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
520 // # fallthrough to sinkMBB
523 // Update machine-CFG edges
524 BB->addSuccessor(sinkMBB);
527 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
531 BuildMI(*BB, BB->begin(), DL,
532 TII->get(Mips::PHI), MI->getOperand(0).getReg())
533 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
534 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
536 MI->eraseFromParent(); // The pseudo instruction is gone now.
541 MachineBasicBlock *Mips16TargetLowering::emitSeliT16
542 (unsigned Opc1, unsigned Opc2,
543 MachineInstr *MI, MachineBasicBlock *BB) const {
544 if (DontExpandCondPseudos16)
546 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
547 DebugLoc DL = MI->getDebugLoc();
548 // To "insert" a SELECT_CC instruction, we actually have to insert the
549 // diamond control-flow pattern. The incoming instruction knows the
550 // destination vreg to set, the condition code register to branch on, the
551 // true/false values to select between, and a branch opcode to use.
552 const BasicBlock *LLVM_BB = BB->getBasicBlock();
553 MachineFunction::iterator It = BB;
560 // bNE r1, r0, copy1MBB
561 // fallthrough --> copy0MBB
562 MachineBasicBlock *thisMBB = BB;
563 MachineFunction *F = BB->getParent();
564 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
565 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
566 F->insert(It, copy0MBB);
567 F->insert(It, sinkMBB);
569 // Transfer the remainder of BB and its successor edges to sinkMBB.
570 sinkMBB->splice(sinkMBB->begin(), BB,
571 llvm::next(MachineBasicBlock::iterator(MI)),
573 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
575 // Next, add the true and fallthrough blocks as its successors.
576 BB->addSuccessor(copy0MBB);
577 BB->addSuccessor(sinkMBB);
579 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
580 .addImm(MI->getOperand(4).getImm());
581 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
585 // # fallthrough to sinkMBB
588 // Update machine-CFG edges
589 BB->addSuccessor(sinkMBB);
592 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
596 BuildMI(*BB, BB->begin(), DL,
597 TII->get(Mips::PHI), MI->getOperand(0).getReg())
598 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
599 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
601 MI->eraseFromParent(); // The pseudo instruction is gone now.
607 *Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
609 MachineBasicBlock *BB) const {
610 if (DontExpandCondPseudos16)
612 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
613 unsigned regX = MI->getOperand(0).getReg();
614 unsigned regY = MI->getOperand(1).getReg();
615 MachineBasicBlock *target = MI->getOperand(2).getMBB();
616 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addReg(regY);
617 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
618 MI->eraseFromParent(); // The pseudo instruction is gone now.
622 MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins(
623 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc,
624 MachineInstr *MI, MachineBasicBlock *BB) const {
625 if (DontExpandCondPseudos16)
627 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
628 unsigned regX = MI->getOperand(0).getReg();
629 int64_t imm = MI->getOperand(1).getImm();
630 MachineBasicBlock *target = MI->getOperand(2).getMBB();
634 else if (isUInt<16>(imm))
637 llvm_unreachable("immediate field not usable");
638 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
639 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
640 MI->eraseFromParent(); // The pseudo instruction is gone now.
644 static unsigned Mips16WhichOp8uOr16simm
645 (unsigned shortOp, unsigned longOp, int64_t Imm) {
648 else if (isInt<16>(Imm))
651 llvm_unreachable("immediate field not usable");
654 MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRX16_ins(
656 MachineInstr *MI, MachineBasicBlock *BB) const {
657 if (DontExpandCondPseudos16)
659 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
660 unsigned CC = MI->getOperand(0).getReg();
661 unsigned regX = MI->getOperand(1).getReg();
662 unsigned regY = MI->getOperand(2).getReg();
663 BuildMI(*BB, MI, MI->getDebugLoc(),
664 TII->get(SltOpc)).addReg(regX).addReg(regY);
665 BuildMI(*BB, MI, MI->getDebugLoc(),
666 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
667 MI->eraseFromParent(); // The pseudo instruction is gone now.
671 MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRXI16_ins(
672 unsigned SltiOpc, unsigned SltiXOpc,
673 MachineInstr *MI, MachineBasicBlock *BB )const {
674 if (DontExpandCondPseudos16)
676 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
677 unsigned CC = MI->getOperand(0).getReg();
678 unsigned regX = MI->getOperand(1).getReg();
679 int64_t Imm = MI->getOperand(2).getImm();
680 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
681 BuildMI(*BB, MI, MI->getDebugLoc(),
682 TII->get(SltOpc)).addReg(regX).addImm(Imm);
683 BuildMI(*BB, MI, MI->getDebugLoc(),
684 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
685 MI->eraseFromParent(); // The pseudo instruction is gone now.