1 //===- Mips16InstrFormats.td - Mips Instruction Formats ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // funct or f Function field
17 // immediate 4-,5-,8- or 11-bit immediate, branch displacemen, or
18 // or imm address displacement
20 // op 5-bit major operation code
22 // rx 3-bit source or destination register
24 // ry 3-bit source or destination register
26 // rz 3-bit source or destination register
28 // sa 3- or 5-bit shift amount
30 //===----------------------------------------------------------------------===//
32 // Format specifies the encoding used by the instruction. This is part of the
33 // ad-hoc solution used to emit machine instruction encodings by our machine
36 class Format16<bits<5> val> {
40 def Pseudo16 : Format16<0>;
41 def FrmI16 : Format16<1>;
42 def FrmRI16 : Format16<2>;
43 def FrmRR16 : Format16<3>;
44 def FrmRRI16 : Format16<4>;
45 def FrmRRR16 : Format16<5>;
46 def FrmRRI_A16 : Format16<6>;
47 def FrmSHIFT16 : Format16<7>;
48 def FrmI8_TYPE16 : Format16<8>;
49 def FrmI8_MOVR3216 : Format16<9>;
50 def FrmI8_MOV32R16 : Format16<10>;
51 def FrmI8_SVRS16 : Format16<11>;
52 def FrmJAL16 : Format16<12>;
53 def FrmJALX16 : Format16<13>;
54 def FrmEXT_I16 : Format16<14>;
55 def FrmASMACRO16 : Format16<15>;
56 def FrmEXT_RI16 : Format16<16>;
57 def FrmEXT_RRI16 : Format16<17>;
58 def FrmEXT_RRI_A16 : Format16<18>;
59 def FrmEXT_SHIFT16 : Format16<19>;
60 def FrmEXT_I816 : Format16<20>;
61 def FrmEXT_I8_SVRS16 : Format16<21>;
62 def FrmOther16 : Format16<22>; // Instruction w/ a custom format
64 // Generic Mips 16 Format
65 class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
66 InstrItinClass itin, Format16 f>: Instruction
71 let Namespace = "Mips";
75 // Top 6 bits are the 'opcode' field
76 let Inst{15-11} = Opcode;
78 let OutOperandList = outs;
79 let InOperandList = ins;
81 let AsmString = asmstr;
82 let Pattern = pattern;
86 // Attributes specific to Mips instructions...
88 bits<5> FormBits = Form.Value;
90 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
91 let TSFlags{4-0} = FormBits;
95 // TBD. Maybe MipsInst16 and Mips16_EXTEND should be derived from a single
99 class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
100 InstrItinClass itin, Format16 f>: Instruction
105 let Namespace = "Mips";
110 // Top 6 bits are the 'opcode' field
111 let Inst{31-27} = extend;
112 let Inst{15-11} = Opcode;
114 let OutOperandList = outs;
115 let InOperandList = ins;
117 let AsmString = asmstr;
118 let Pattern = pattern;
119 let Itinerary = itin;
122 // Attributes specific to Mips instructions...
124 bits<5> FormBits = Form.Value;
126 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
127 let TSFlags{4-0} = FormBits;
132 // Mips Pseudo Instructions Format
133 class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
134 MipsInst16<outs, ins, asmstr, pattern, IIPseudo, Pseudo16> {
135 let isCodeGenOnly = 1;
140 //===----------------------------------------------------------------------===//
141 // Format I instruction class in Mips : <|opcode|immediate|>
142 //===----------------------------------------------------------------------===//
144 class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
145 InstrItinClass itin>: MipsInst16<outs, ins, asmstr, pattern,
152 let Inst{10-0} = imm11;
155 //===----------------------------------------------------------------------===//
156 // Format RI instruction class in Mips : <|opcode|rx|immed|>
157 //===----------------------------------------------------------------------===//
159 class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
160 list<dag> pattern, InstrItinClass itin>:
161 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRI16>
169 let Inst{7-0} = imm8;
172 //===----------------------------------------------------------------------===//
173 // Format RR instruction class in Mips : <|opcode|rx|ry|funct|>
174 //===----------------------------------------------------------------------===//
176 class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
177 list<dag> pattern, InstrItinClass itin>:
178 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
184 let Opcode = 0b11101;
189 let Inst{4-0} = funct;
192 //===----------------------------------------------------------------------===//
193 // Format RRI instruction class in Mips : <|opcode|rx|ry|immed|>
194 //===----------------------------------------------------------------------===//
196 class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,
197 list<dag> pattern, InstrItinClass itin>:
198 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRI16>
209 let Inst{4-0} = imm5;
212 //===----------------------------------------------------------------------===//
213 // Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|>
214 //===----------------------------------------------------------------------===//
216 class FRRR16<bits<5> op, bits<2> _f, dag outs, dag ins, string asmstr,
217 list<dag> pattern, InstrItinClass itin>:
218 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRR16>
234 //===----------------------------------------------------------------------===//
235 // Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|immed|>
236 //===----------------------------------------------------------------------===//
238 class FRRI_A16<bits<5> op, bits<1> _f, dag outs, dag ins, string asmstr,
239 list<dag> pattern, InstrItinClass itin>:
240 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRI_A16>
253 let Inst{3-0} = imm4;
256 //===----------------------------------------------------------------------===//
257 // Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|>
258 //===----------------------------------------------------------------------===//
260 class FSHIFT16<bits<5> op, bits<2> _f, dag outs, dag ins, string asmstr,
261 list<dag> pattern, InstrItinClass itin>:
262 MipsInst16<outs, ins, asmstr, pattern, itin, FrmSHIFT16>
278 //===----------------------------------------------------------------------===//
279 // Format i8 instruction class in Mips : <|opcode|funct|immed>
280 //===----------------------------------------------------------------------===//
282 class FI816<bits<5> op, bits<3> _func, dag outs, dag ins, string asmstr,
283 list<dag> pattern, InstrItinClass itin>:
284 MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_TYPE16>
292 let Inst{10-8} = func;
293 let Inst{7-0} = immed8;
296 //===----------------------------------------------------------------------===//
297 // Format i8_MOVR32 instruction class in Mips : <|opcode|func|ry|r32>
298 //===----------------------------------------------------------------------===//
300 class FI8_MOVR3216<bits<5> op, bits<3> _func, dag outs, dag ins, string asmstr,
301 list<dag> pattern, InstrItinClass itin>:
302 MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_MOVR3216>
312 let Inst{10-8} = func;
320 //===----------------------------------------------------------------------===//
321 // Format i8_MOV32R instruction class in Mips : <|opcode|func|ry|r32>
322 //===----------------------------------------------------------------------===//
324 class FI8_MOV32R16<bits<5> op, bits<3> _func, dag outs, dag ins, string asmstr,
325 list<dag> pattern, InstrItinClass itin>:
326 MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_MOV32R16>
337 let Inst{10-8} = func;
338 let Inst{7-5} = r32{2-0};
339 let Inst{4-3} = r32{4-3};
344 //===----------------------------------------------------------------------===//
345 // Format i8_SVRS instruction class in Mips :
346 // <|opcode|svrs|s|ra|s0|s1|framesize>
347 //===----------------------------------------------------------------------===//
349 class FI8_SVRS16<bits<5> op, bits<3> _SVRS, dag outs, dag ins, string asmstr,
350 list<dag> pattern, InstrItinClass itin>:
351 MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_SVRS16>
363 let Inst{10-8} = SVRS;
368 let Inst{3-0} = framesize;
372 //===----------------------------------------------------------------------===//
373 // Format JAL instruction class in Mips16 :
374 // <|opcode|svrs|s|ra|s0|s1|framesize>
375 //===----------------------------------------------------------------------===//
377 class FJAL16<bits<5> op, bits<1> _X, dag outs, dag ins, string asmstr,
378 list<dag> pattern, InstrItinClass itin>:
379 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmJAL16>
389 let Inst{25-21} = immed26{20-16};
390 let Inst{20-16} = immed26{25-21};
391 let Inst{15-0} = immed26{15-0};
396 //===----------------------------------------------------------------------===//
397 // Format EXT-I instruction class in Mips16 :
398 // <|opcode|immed10:5|immed15:1|op|0|0|0|0|0|0|immed4:0>
399 //===----------------------------------------------------------------------===//
401 class FEXT_I16<bits<5> op, bits<5> _eop, dag outs, dag ins, string asmstr,
402 list<dag> pattern, InstrItinClass itin>:
403 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_I16>
411 let Inst{26-21} = immed16{10-5};
412 let Inst{20-16} = immed16{15-11};
413 let Inst{15-11} = eop;
415 let Inst{4-0} = immed16{4-0};
424 //===----------------------------------------------------------------------===//
425 // Format ASMACRO instruction class in Mips16 :
426 // <EXTEND|select|p4|p3|RRR|p2|p1|p0>
427 //===----------------------------------------------------------------------===//
429 class FASMACRO16<bits<5> op, dag outs, dag ins, string asmstr,
430 list<dag> pattern, InstrItinClass itin>:
431 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
444 let Inst{26-24} = select;
445 let Inst{23-21} = p4;
446 let Inst{20-16} = p3;
447 let Inst{15-11} = RRR;
455 //===----------------------------------------------------------------------===//
456 // Format EXT-RI instruction class in Mips16 :
457 // <|opcode|immed10:5|immed15:11|op|rx|0|0|0|immed4:0>
458 //===----------------------------------------------------------------------===//
460 class FEXT_RI16<bits<5> op, bits<5> _eop, dag outs, dag ins, string asmstr,
461 list<dag> pattern, InstrItinClass itin>:
462 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
472 let Inst{26-21} = immed16{10-5};
473 let Inst{20-16} = immed16{15-11};
474 let Inst{15-11} = eop;
477 let Inst{4-0} = immed16{4-0};
481 //===----------------------------------------------------------------------===//
482 // Format EXT-RRI instruction class in Mips16 :
483 // <|opcode|immed10:5|immed15:11|op|rx|ry|immed4:0>
484 //===----------------------------------------------------------------------===//
486 class FEXT_RRI16<bits<5> op, bits<5> _eop, dag outs, dag ins, string asmstr,
487 list<dag> pattern, InstrItinClass itin>:
488 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
499 let Inst{26-21} = immed16{10-5};
500 let Inst{20-16} = immed16{15-11};
501 let Inst{15-11} = eop;
504 let Inst{4-0} = immed16{4-0};
508 //===----------------------------------------------------------------------===//
509 // Format EXT-RRI-A instruction class in Mips16 :
510 // <|opcode|immed10:4|immed14:11|RRI-A|rx|ry|f|immed3:0>
511 //===----------------------------------------------------------------------===//
513 class FEXT_RRI_A16<bits<5> op, bits<1> _f, dag outs, dag ins, string asmstr,
514 list<dag> pattern, InstrItinClass itin>:
515 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
527 let Inst{26-20} = immed15{10-4};
528 let Inst{19-16} = immed15{14-11};
529 let Inst{15-11} = RRI_A;
533 let Inst{3-0} = immed15{3-0};
537 //===----------------------------------------------------------------------===//
538 // Format EXT-SHIFT instruction class in Mips16 :
539 // <|opcode|sa 4:0|s5|0|SHIFT|rx|ry|0|f>
540 //===----------------------------------------------------------------------===//
542 class FEXT_SHIFT16<bits<5> op, bits<2> _f, dag outs, dag ins, string asmstr,
543 list<dag> pattern, InstrItinClass itin>:
544 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
556 let Inst{26-22} = sa6{4-0};
557 let Inst{21} = sa6{5};
559 let Inst{15-11} = shift;
567 //===----------------------------------------------------------------------===//
568 // Format EXT-I8 instruction class in Mips16 :
569 // <|opcode|immed10:5|immed15:11|I8|funct|0|immed4:0>
570 //===----------------------------------------------------------------------===//
572 class FEXT_I816<bits<5> op, bits<3> _funct, dag outs, dag ins, string asmstr,
573 list<dag> pattern, InstrItinClass itin>:
574 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
584 let Inst{26-21} = immed16{10-5};
585 let Inst{20-16} = immed16{15-11};
586 let Inst{15-11} = I8;
587 let Inst{10-8} = funct;
589 let Inst{4-0} = immed16{4-0};
593 //===----------------------------------------------------------------------===//
594 // Format EXT-I8_SVRS instruction class in Mips16 :
595 // <|opcode|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0>
596 //===----------------------------------------------------------------------===//
598 class FEXT_I8_SVRS16<bits<5> op, dag outs, dag ins, string asmstr,
599 list<dag> pattern, InstrItinClass itin>:
600 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
615 let Inst{26-24} = xsregs;
616 let Inst{23-20} = framesize{7-4};
618 let Inst{18-16} = aregs;
619 let Inst{15-11} = I8;
620 let Inst{10-8} = SVRS;
625 let Inst{3-0} = framesize{3-0};