1 //===- Mips16InstrFormats.td - Mips Instruction Formats ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // funct or f Function field
17 // immediate 4-,5-,8- or 11-bit immediate, branch displacement, or
18 // or imm address displacement
20 // op 5-bit major operation code
22 // rx 3-bit source or destination register
24 // ry 3-bit source or destination register
26 // rz 3-bit source or destination register
28 // sa 3- or 5-bit shift amount
30 //===----------------------------------------------------------------------===//
33 // Base class for Mips 16 Format
34 // This class does not depend on the instruction size
36 class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
37 InstrItinClass itin>: Instruction
40 let Namespace = "Mips";
42 let OutOperandList = outs;
43 let InOperandList = ins;
45 let AsmString = asmstr;
46 let Pattern = pattern;
49 let Predicates = [InMips16Mode];
53 // Generic Mips 16 Format
55 class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
57 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
62 // Top 5 bits are the 'opcode' field
63 let Inst{15-11} = Opcode;
66 field bits<16> SoftFail = 0;
70 // For 32 bit extended instruction forms.
72 class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
74 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
79 field bits<32> SoftFail = 0;
82 class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
84 MipsInst16_32<outs, ins, asmstr, pattern, itin>
86 let Inst{31-27} = 0b11110;
91 // Mips Pseudo Instructions Format
92 class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
93 MipsInst16<outs, ins, asmstr, pattern, IIPseudo> {
94 let isCodeGenOnly = 1;
99 //===----------------------------------------------------------------------===//
100 // Format I instruction class in Mips : <|opcode|imm11|>
101 //===----------------------------------------------------------------------===//
103 class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
104 InstrItinClass itin>:
105 MipsInst16<outs, ins, asmstr, pattern, itin>
111 let Inst{10-0} = imm11;
114 //===----------------------------------------------------------------------===//
115 // Format RI instruction class in Mips : <|opcode|rx|imm8|>
116 //===----------------------------------------------------------------------===//
118 class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
119 list<dag> pattern, InstrItinClass itin>:
120 MipsInst16<outs, ins, asmstr, pattern, itin>
128 let Inst{7-0} = imm8;
131 //===----------------------------------------------------------------------===//
132 // Format RR instruction class in Mips : <|opcode|rx|ry|funct|>
133 //===----------------------------------------------------------------------===//
135 class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
136 list<dag> pattern, InstrItinClass itin>:
137 MipsInst16<outs, ins, asmstr, pattern, itin>
143 let Opcode = 0b11101;
148 let Inst{4-0} = funct;
152 // For conversion functions.
154 class FRR_SF16<bits<5> _funct, bits<3> _subfunct, dag outs, dag ins,
155 string asmstr, list<dag> pattern, InstrItinClass itin>:
156 MipsInst16<outs, ins, asmstr, pattern, itin>
162 let Opcode = 0b11101; // RR
164 let subfunct = _subfunct;
167 let Inst{7-5} = subfunct;
168 let Inst{4-0} = funct;
172 // just used for breakpoint (hardware and software) instructions.
174 class FC16<bits<5> _funct, dag outs, dag ins, string asmstr,
175 list<dag> pattern, InstrItinClass itin>:
176 MipsInst16<outs, ins, asmstr, pattern, itin>
178 bits<6> _code; // code is a keyword in tablegen
181 let Opcode = 0b11101; // RR
184 let Inst{10-5} = _code;
185 let Inst{4-0} = funct;
189 // J(AL)R(C) subformat
191 class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a,
192 dag outs, dag ins, string asmstr,
193 list<dag> pattern, InstrItinClass itin>:
194 MipsInst16<outs, ins, asmstr, pattern, itin>
205 let Opcode = 0b11101;
214 //===----------------------------------------------------------------------===//
215 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
216 //===----------------------------------------------------------------------===//
218 class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,
219 list<dag> pattern, InstrItinClass itin>:
220 MipsInst16<outs, ins, asmstr, pattern, itin>
231 let Inst{4-0} = imm5;
234 //===----------------------------------------------------------------------===//
235 // Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|>
236 //===----------------------------------------------------------------------===//
238 class FRRR16<bits<2> _f, dag outs, dag ins, string asmstr,
239 list<dag> pattern, InstrItinClass itin>:
240 MipsInst16<outs, ins, asmstr, pattern, itin>
247 let Opcode = 0b11100;
256 //===----------------------------------------------------------------------===//
257 // Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
258 //===----------------------------------------------------------------------===//
260 class FRRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
261 list<dag> pattern, InstrItinClass itin>:
262 MipsInst16<outs, ins, asmstr, pattern, itin>
269 let Opcode = 0b01000;
275 let Inst{3-0} = imm4;
278 //===----------------------------------------------------------------------===//
279 // Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|>
280 //===----------------------------------------------------------------------===//
282 class FSHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
283 list<dag> pattern, InstrItinClass itin>:
284 MipsInst16<outs, ins, asmstr, pattern, itin>
291 let Opcode = 0b00110;
300 //===----------------------------------------------------------------------===//
301 // Format i8 instruction class in Mips : <|opcode|funct|imm8>
302 //===----------------------------------------------------------------------===//
304 class FI816<bits<3> _func, dag outs, dag ins, string asmstr,
305 list<dag> pattern, InstrItinClass itin>:
306 MipsInst16<outs, ins, asmstr, pattern, itin>
311 let Opcode = 0b01100;
314 let Inst{10-8} = func;
315 let Inst{7-0} = imm8;
318 //===----------------------------------------------------------------------===//
319 // Format i8_MOVR32 instruction class in Mips : <|opcode|func|ry|r32>
320 //===----------------------------------------------------------------------===//
322 class FI8_MOVR3216<dag outs, dag ins, string asmstr,
323 list<dag> pattern, InstrItinClass itin>:
324 MipsInst16<outs, ins, asmstr, pattern, itin>
330 let Opcode = 0b01100;
332 let Inst{10-8} = 0b111;
340 //===----------------------------------------------------------------------===//
341 // Format i8_MOV32R instruction class in Mips : <|opcode|func|r32|rz>
342 //===----------------------------------------------------------------------===//
344 class FI8_MOV32R16<dag outs, dag ins, string asmstr,
345 list<dag> pattern, InstrItinClass itin>:
346 MipsInst16<outs, ins, asmstr, pattern, itin>
354 let Opcode = 0b01100;
356 let Inst{10-8} = 0b101;
357 let Inst{7-5} = r32{2-0};
358 let Inst{4-3} = r32{4-3};
363 //===----------------------------------------------------------------------===//
364 // Format i8_SVRS instruction class in Mips :
365 // <|opcode|svrs|s|ra|s0|s1|framesize>
366 //===----------------------------------------------------------------------===//
368 class FI8_SVRS16<bits<1> _s, dag outs, dag ins, string asmstr,
369 list<dag> pattern, InstrItinClass itin>:
370 MipsInst16<outs, ins, asmstr, pattern, itin>
376 bits<4> framesize = 0;
379 let Opcode = 0b01100;
381 let Inst{10-8} = 0b100;
386 let Inst{3-0} = framesize;
390 //===----------------------------------------------------------------------===//
391 // Format JAL instruction class in Mips16 :
392 // <|opcode|svrs|s|ra|s0|s1|framesize>
393 //===----------------------------------------------------------------------===//
395 class FJAL16<bits<1> _X, dag outs, dag ins, string asmstr,
396 list<dag> pattern, InstrItinClass itin>:
397 MipsInst16_32<outs, ins, asmstr, pattern, itin>
405 let Inst{31-27} = 0b00011;
407 let Inst{25-21} = imm26{20-16};
408 let Inst{20-16} = imm26{25-21};
409 let Inst{15-0} = imm26{15-0};
413 //===----------------------------------------------------------------------===//
414 // Format EXT-I instruction class in Mips16 :
415 // <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
416 //===----------------------------------------------------------------------===//
418 class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,
419 list<dag> pattern, InstrItinClass itin>:
420 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
427 let Inst{26-21} = imm16{10-5};
428 let Inst{20-16} = imm16{15-11};
429 let Inst{15-11} = eop;
431 let Inst{4-0} = imm16{4-0};
435 //===----------------------------------------------------------------------===//
436 // Format ASMACRO instruction class in Mips16 :
437 // <EXTEND|select|p4|p3|RRR|p2|p1|p0>
438 //===----------------------------------------------------------------------===//
440 class FASMACRO16<dag outs, dag ins, string asmstr,
441 list<dag> pattern, InstrItinClass itin>:
442 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
447 bits<5> RRR = 0b11100;
453 let Inst{26-24} = select;
454 let Inst{23-21} = p4;
455 let Inst{20-16} = p3;
456 let Inst{15-11} = RRR;
464 //===----------------------------------------------------------------------===//
465 // Format EXT-RI instruction class in Mips16 :
466 // <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
467 //===----------------------------------------------------------------------===//
469 class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,
470 list<dag> pattern, InstrItinClass itin>:
471 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
479 let Inst{26-21} = imm16{10-5};
480 let Inst{20-16} = imm16{15-11};
481 let Inst{15-11} = op;
484 let Inst{4-0} = imm16{4-0};
488 //===----------------------------------------------------------------------===//
489 // Format EXT-RRI instruction class in Mips16 :
490 // <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
491 //===----------------------------------------------------------------------===//
493 class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr,
494 list<dag> pattern, InstrItinClass itin>:
495 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
504 let Inst{26-21} = imm16{10-5};
505 let Inst{20-16} = imm16{15-11};
506 let Inst{15-11} = op;
509 let Inst{4-0} = imm16{4-0};
513 //===----------------------------------------------------------------------===//
514 // Format EXT-RRI-A instruction class in Mips16 :
515 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
516 //===----------------------------------------------------------------------===//
518 class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
519 list<dag> pattern, InstrItinClass itin>:
520 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
529 let Inst{26-20} = imm15{10-4};
530 let Inst{19-16} = imm15{14-11};
531 let Inst{15-11} = 0b01000;
535 let Inst{3-0} = imm15{3-0};
539 //===----------------------------------------------------------------------===//
540 // Format EXT-SHIFT instruction class in Mips16 :
541 // <|EXTEND|sa 4:0|s5|0|SHIFT|rx|ry|0|f>
542 //===----------------------------------------------------------------------===//
544 class FEXT_SHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
545 list<dag> pattern, InstrItinClass itin>:
546 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
555 let Inst{26-22} = sa6{4-0};
556 let Inst{21} = sa6{5};
558 let Inst{15-11} = 0b00110;
566 //===----------------------------------------------------------------------===//
567 // Format EXT-I8 instruction class in Mips16 :
568 // <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
569 //===----------------------------------------------------------------------===//
571 class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,
572 list<dag> pattern, InstrItinClass itin>:
573 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
582 let Inst{26-21} = imm16{10-5};
583 let Inst{20-16} = imm16{15-11};
584 let Inst{15-11} = I8;
585 let Inst{10-8} = funct;
587 let Inst{4-0} = imm16{4-0};
591 //===----------------------------------------------------------------------===//
592 // Format EXT-I8_SVRS instruction class in Mips16 :
593 // <|EXTEND|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0>
594 //===----------------------------------------------------------------------===//
596 class FEXT_I8_SVRS16<bits<1> s_, dag outs, dag ins, string asmstr,
597 list<dag> pattern, InstrItinClass itin>:
598 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
601 bits<8> framesize =0;
603 bits<5> I8 = 0b01100;
604 bits<3> SVRS = 0b100;
612 let Inst{26-24} = xsregs;
613 let Inst{23-20} = framesize{7-4};
615 let Inst{18-16} = aregs;
616 let Inst{15-11} = I8;
617 let Inst{10-8} = SVRS;
622 let Inst{3-0} = framesize{3-0};