1 //===- Mips16InstrFormats.td - Mips Instruction Formats ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // funct or f Function field
17 // immediate 4-,5-,8- or 11-bit immediate, branch displacement, or
18 // or imm address displacement
20 // op 5-bit major operation code
22 // rx 3-bit source or destination register
24 // ry 3-bit source or destination register
26 // rz 3-bit source or destination register
28 // sa 3- or 5-bit shift amount
30 //===----------------------------------------------------------------------===//
33 // Base class for Mips 16 Format
34 // This class does not depend on the instruction size
36 class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
37 InstrItinClass itin>: Instruction
40 let Namespace = "Mips";
42 let OutOperandList = outs;
43 let InOperandList = ins;
45 let AsmString = asmstr;
46 let Pattern = pattern;
49 let Predicates = [InMips16Mode];
53 // Generic Mips 16 Format
55 class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
57 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
62 // Top 5 bits are the 'opcode' field
63 let Inst{15-11} = Opcode;
66 field bits<16> SoftFail = 0;
70 // For 32 bit extended instruction forms.
72 class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
74 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
79 field bits<32> SoftFail = 0;
82 class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
84 MipsInst16_32<outs, ins, asmstr, pattern, itin>
86 let Inst{31-27} = 0b11110;
91 // Mips Pseudo Instructions Format
92 class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
93 MipsInst16<outs, ins, asmstr, pattern, IIPseudo> {
94 let isCodeGenOnly = 1;
99 //===----------------------------------------------------------------------===//
100 // Format I instruction class in Mips : <|opcode|imm11|>
101 //===----------------------------------------------------------------------===//
103 class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
104 InstrItinClass itin>:
105 MipsInst16<outs, ins, asmstr, pattern, itin>
111 let Inst{10-0} = imm11;
114 //===----------------------------------------------------------------------===//
115 // Format RI instruction class in Mips : <|opcode|rx|imm8|>
116 //===----------------------------------------------------------------------===//
118 class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
119 list<dag> pattern, InstrItinClass itin>:
120 MipsInst16<outs, ins, asmstr, pattern, itin>
128 let Inst{7-0} = imm8;
131 //===----------------------------------------------------------------------===//
132 // Format RR instruction class in Mips : <|opcode|rx|ry|funct|>
133 //===----------------------------------------------------------------------===//
135 class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
136 list<dag> pattern, InstrItinClass itin>:
137 MipsInst16<outs, ins, asmstr, pattern, itin>
143 let Opcode = 0b11101;
148 let Inst{4-0} = funct;
151 class FRRBreak16<dag outs, dag ins, string asmstr,
152 list<dag> pattern, InstrItinClass itin>:
153 MipsInst16<outs, ins, asmstr, pattern, itin>
158 let Opcode = 0b11101;
161 let Inst{10-5} = Code;
162 let Inst{4-0} = funct;
166 // For conversion functions.
168 class FRR_SF16<bits<5> _funct, bits<3> _subfunct, dag outs, dag ins,
169 string asmstr, list<dag> pattern, InstrItinClass itin>:
170 MipsInst16<outs, ins, asmstr, pattern, itin>
176 let Opcode = 0b11101; // RR
178 let subfunct = _subfunct;
181 let Inst{7-5} = subfunct;
182 let Inst{4-0} = funct;
186 // just used for breakpoint (hardware and software) instructions.
188 class FC16<bits<5> _funct, dag outs, dag ins, string asmstr,
189 list<dag> pattern, InstrItinClass itin>:
190 MipsInst16<outs, ins, asmstr, pattern, itin>
192 bits<6> _code; // code is a keyword in tablegen
195 let Opcode = 0b11101; // RR
198 let Inst{10-5} = _code;
199 let Inst{4-0} = funct;
203 // J(AL)R(C) subformat
205 class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a,
206 dag outs, dag ins, string asmstr,
207 list<dag> pattern, InstrItinClass itin>:
208 MipsInst16<outs, ins, asmstr, pattern, itin>
219 let Opcode = 0b11101;
228 //===----------------------------------------------------------------------===//
229 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
230 //===----------------------------------------------------------------------===//
232 class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,
233 list<dag> pattern, InstrItinClass itin>:
234 MipsInst16<outs, ins, asmstr, pattern, itin>
245 let Inst{4-0} = imm5;
248 //===----------------------------------------------------------------------===//
249 // Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|>
250 //===----------------------------------------------------------------------===//
252 class FRRR16<bits<2> _f, dag outs, dag ins, string asmstr,
253 list<dag> pattern, InstrItinClass itin>:
254 MipsInst16<outs, ins, asmstr, pattern, itin>
261 let Opcode = 0b11100;
270 //===----------------------------------------------------------------------===//
271 // Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
272 //===----------------------------------------------------------------------===//
274 class FRRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
275 list<dag> pattern, InstrItinClass itin>:
276 MipsInst16<outs, ins, asmstr, pattern, itin>
283 let Opcode = 0b01000;
289 let Inst{3-0} = imm4;
292 //===----------------------------------------------------------------------===//
293 // Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|>
294 //===----------------------------------------------------------------------===//
296 class FSHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
297 list<dag> pattern, InstrItinClass itin>:
298 MipsInst16<outs, ins, asmstr, pattern, itin>
305 let Opcode = 0b00110;
314 //===----------------------------------------------------------------------===//
315 // Format i8 instruction class in Mips : <|opcode|funct|imm8>
316 //===----------------------------------------------------------------------===//
318 class FI816<bits<3> _func, dag outs, dag ins, string asmstr,
319 list<dag> pattern, InstrItinClass itin>:
320 MipsInst16<outs, ins, asmstr, pattern, itin>
325 let Opcode = 0b01100;
328 let Inst{10-8} = func;
329 let Inst{7-0} = imm8;
332 //===----------------------------------------------------------------------===//
333 // Format i8_MOVR32 instruction class in Mips : <|opcode|func|ry|r32>
334 //===----------------------------------------------------------------------===//
336 class FI8_MOVR3216<dag outs, dag ins, string asmstr,
337 list<dag> pattern, InstrItinClass itin>:
338 MipsInst16<outs, ins, asmstr, pattern, itin>
344 let Opcode = 0b01100;
346 let Inst{10-8} = 0b111;
354 //===----------------------------------------------------------------------===//
355 // Format i8_MOV32R instruction class in Mips : <|opcode|func|r32|rz>
356 //===----------------------------------------------------------------------===//
358 class FI8_MOV32R16<dag outs, dag ins, string asmstr,
359 list<dag> pattern, InstrItinClass itin>:
360 MipsInst16<outs, ins, asmstr, pattern, itin>
368 let Opcode = 0b01100;
370 let Inst{10-8} = 0b101;
371 let Inst{7-5} = r32{2-0};
372 let Inst{4-3} = r32{4-3};
377 //===----------------------------------------------------------------------===//
378 // Format i8_SVRS instruction class in Mips :
379 // <|opcode|svrs|s|ra|s0|s1|framesize>
380 //===----------------------------------------------------------------------===//
382 class FI8_SVRS16<bits<1> _s, dag outs, dag ins, string asmstr,
383 list<dag> pattern, InstrItinClass itin>:
384 MipsInst16<outs, ins, asmstr, pattern, itin>
390 bits<4> framesize = 0;
393 let Opcode = 0b01100;
395 let Inst{10-8} = 0b100;
400 let Inst{3-0} = framesize;
404 //===----------------------------------------------------------------------===//
405 // Format JAL instruction class in Mips16 :
406 // <|opcode|svrs|s|ra|s0|s1|framesize>
407 //===----------------------------------------------------------------------===//
409 class FJAL16<bits<1> _X, dag outs, dag ins, string asmstr,
410 list<dag> pattern, InstrItinClass itin>:
411 MipsInst16_32<outs, ins, asmstr, pattern, itin>
419 let Inst{31-27} = 0b00011;
421 let Inst{25-21} = imm26{20-16};
422 let Inst{20-16} = imm26{25-21};
423 let Inst{15-0} = imm26{15-0};
427 //===----------------------------------------------------------------------===//
428 // Format EXT-I instruction class in Mips16 :
429 // <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
430 //===----------------------------------------------------------------------===//
432 class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,
433 list<dag> pattern, InstrItinClass itin>:
434 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
441 let Inst{26-21} = imm16{10-5};
442 let Inst{20-16} = imm16{15-11};
443 let Inst{15-11} = eop;
445 let Inst{4-0} = imm16{4-0};
449 //===----------------------------------------------------------------------===//
450 // Format ASMACRO instruction class in Mips16 :
451 // <EXTEND|select|p4|p3|RRR|p2|p1|p0>
452 //===----------------------------------------------------------------------===//
454 class FASMACRO16<dag outs, dag ins, string asmstr,
455 list<dag> pattern, InstrItinClass itin>:
456 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
461 bits<5> RRR = 0b11100;
467 let Inst{26-24} = select;
468 let Inst{23-21} = p4;
469 let Inst{20-16} = p3;
470 let Inst{15-11} = RRR;
478 //===----------------------------------------------------------------------===//
479 // Format EXT-RI instruction class in Mips16 :
480 // <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
481 //===----------------------------------------------------------------------===//
483 class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,
484 list<dag> pattern, InstrItinClass itin>:
485 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
493 let Inst{26-21} = imm16{10-5};
494 let Inst{20-16} = imm16{15-11};
495 let Inst{15-11} = op;
498 let Inst{4-0} = imm16{4-0};
502 //===----------------------------------------------------------------------===//
503 // Format EXT-RRI instruction class in Mips16 :
504 // <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
505 //===----------------------------------------------------------------------===//
507 class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr,
508 list<dag> pattern, InstrItinClass itin>:
509 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
518 let Inst{26-21} = imm16{10-5};
519 let Inst{20-16} = imm16{15-11};
520 let Inst{15-11} = op;
523 let Inst{4-0} = imm16{4-0};
527 //===----------------------------------------------------------------------===//
528 // Format EXT-RRI-A instruction class in Mips16 :
529 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
530 //===----------------------------------------------------------------------===//
532 class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
533 list<dag> pattern, InstrItinClass itin>:
534 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
543 let Inst{26-20} = imm15{10-4};
544 let Inst{19-16} = imm15{14-11};
545 let Inst{15-11} = 0b01000;
549 let Inst{3-0} = imm15{3-0};
553 //===----------------------------------------------------------------------===//
554 // Format EXT-SHIFT instruction class in Mips16 :
555 // <|EXTEND|sa 4:0|s5|0|SHIFT|rx|ry|0|f>
556 //===----------------------------------------------------------------------===//
558 class FEXT_SHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
559 list<dag> pattern, InstrItinClass itin>:
560 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
569 let Inst{26-22} = sa6{4-0};
570 let Inst{21} = sa6{5};
572 let Inst{15-11} = 0b00110;
580 //===----------------------------------------------------------------------===//
581 // Format EXT-I8 instruction class in Mips16 :
582 // <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
583 //===----------------------------------------------------------------------===//
585 class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,
586 list<dag> pattern, InstrItinClass itin>:
587 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
596 let Inst{26-21} = imm16{10-5};
597 let Inst{20-16} = imm16{15-11};
598 let Inst{15-11} = I8;
599 let Inst{10-8} = funct;
601 let Inst{4-0} = imm16{4-0};
605 //===----------------------------------------------------------------------===//
606 // Format EXT-I8_SVRS instruction class in Mips16 :
607 // <|EXTEND|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0>
608 //===----------------------------------------------------------------------===//
610 class FEXT_I8_SVRS16<bits<1> s_, dag outs, dag ins, string asmstr,
611 list<dag> pattern, InstrItinClass itin>:
612 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
615 bits<8> framesize =0;
617 bits<5> I8 = 0b01100;
618 bits<3> SVRS = 0b100;
626 let Inst{26-24} = xsregs;
627 let Inst{23-20} = framesize{7-4};
629 let Inst{18-16} = aregs;
630 let Inst{15-11} = I8;
631 let Inst{10-8} = SVRS;
636 let Inst{3-0} = framesize{3-0};