1 //===- Mips16InstrFormats.td - Mips Instruction Formats ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // funct or f Function field
17 // immediate 4-,5-,8- or 11-bit immediate, branch displacemen, or
18 // or imm address displacement
20 // op 5-bit major operation code
22 // rx 3-bit source or destination register
24 // ry 3-bit source or destination register
26 // rz 3-bit source or destination register
28 // sa 3- or 5-bit shift amount
30 //===----------------------------------------------------------------------===//
32 // Format specifies the encoding used by the instruction. This is part of the
33 // ad-hoc solution used to emit machine instruction encodings by our machine
36 class Format16<bits<5> val> {
40 def Pseudo16 : Format16<0>;
41 def FrmI16 : Format16<1>;
42 def FrmRI16 : Format16<2>;
43 def FrmRR16 : Format16<3>;
44 def FrmRRI16 : Format16<4>;
45 def FrmRRR16 : Format16<5>;
46 def FrmRRI_A16 : Format16<6>;
47 def FrmSHIFT16 : Format16<7>;
48 def FrmI8_TYPE16 : Format16<8>;
49 def FrmI8_MOVR3216 : Format16<9>;
50 def FrmI8_MOV32R16 : Format16<10>;
51 def FrmI8_SVRS16 : Format16<11>;
52 def FrmJAL16 : Format16<12>;
53 def FrmJALX16 : Format16<13>;
54 def FrmEXT_I16 : Format16<14>;
55 def FrmASMACRO16 : Format16<15>;
56 def FrmEXT_RI16 : Format16<16>;
57 def FrmEXT_RRI16 : Format16<17>;
58 def FrmEXT_RRI_A16 : Format16<18>;
59 def FrmEXT_SHIFT16 : Format16<19>;
60 def FrmEXT_I816 : Format16<20>;
61 def FrmEXT_I8_SVRS16 : Format16<21>;
62 def FrmOther16 : Format16<22>; // Instruction w/ a custom format
64 // Base class for Mips 16 Format
65 // This class does not depend on the instruction size
67 class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
68 InstrItinClass itin, Format16 f>: Instruction
72 let Namespace = "Mips";
75 let OutOperandList = outs;
76 let InOperandList = ins;
78 let AsmString = asmstr;
79 let Pattern = pattern;
83 // Attributes specific to Mips instructions...
85 bits<5> FormBits = Form.Value;
87 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
88 let TSFlags{4-0} = FormBits;
90 let Predicates = [InMips16Mode];
94 // Generic Mips 16 Format
96 class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
97 InstrItinClass itin, Format16 f>:
98 MipsInst16_Base<outs, ins, asmstr, pattern, itin, f>
103 // Top 6 bits are the 'opcode' field
104 let Inst{15-11} = Opcode;
108 // For 32 bit extended instruction forms.
110 class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
111 InstrItinClass itin, Format16 f>:
112 MipsInst16_Base<outs, ins, asmstr, pattern, itin, f>
118 class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
119 InstrItinClass itin, Format16 f>:
120 MipsInst16_32<outs, ins, asmstr, pattern, itin, f>
123 let Inst{31-27} = 0b11110;
129 // Mips Pseudo Instructions Format
130 class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
131 MipsInst16<outs, ins, asmstr, pattern, IIPseudo, Pseudo16> {
132 let isCodeGenOnly = 1;
137 //===----------------------------------------------------------------------===//
138 // Format I instruction class in Mips : <|opcode|imm11|>
139 //===----------------------------------------------------------------------===//
141 class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
142 InstrItinClass itin>: MipsInst16<outs, ins, asmstr, pattern,
149 let Inst{10-0} = imm11;
152 //===----------------------------------------------------------------------===//
153 // Format RI instruction class in Mips : <|opcode|rx|imm8|>
154 //===----------------------------------------------------------------------===//
156 class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
157 list<dag> pattern, InstrItinClass itin>:
158 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRI16>
166 let Inst{7-0} = imm8;
169 //===----------------------------------------------------------------------===//
170 // Format RR instruction class in Mips : <|opcode|rx|ry|funct|>
171 //===----------------------------------------------------------------------===//
173 class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
174 list<dag> pattern, InstrItinClass itin>:
175 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
181 let Opcode = 0b11101;
186 let Inst{4-0} = funct;
191 // J(AL)R(C) subformat
193 class FRR16_JALRC<dag outs, dag ins, string asmstr,
194 list<dag> pattern, InstrItinClass itin>:
195 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
202 let Opcode = 0b11101;
211 //===----------------------------------------------------------------------===//
212 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
213 //===----------------------------------------------------------------------===//
215 class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,
216 list<dag> pattern, InstrItinClass itin>:
217 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRI16>
228 let Inst{4-0} = imm5;
231 //===----------------------------------------------------------------------===//
232 // Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|>
233 //===----------------------------------------------------------------------===//
235 class FRRR16<bits<5> op, bits<2> _f, dag outs, dag ins, string asmstr,
236 list<dag> pattern, InstrItinClass itin>:
237 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRR16>
253 //===----------------------------------------------------------------------===//
254 // Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
255 //===----------------------------------------------------------------------===//
257 class FRRI_A16<bits<5> op, bits<1> _f, dag outs, dag ins, string asmstr,
258 list<dag> pattern, InstrItinClass itin>:
259 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRI_A16>
272 let Inst{3-0} = imm4;
275 //===----------------------------------------------------------------------===//
276 // Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|>
277 //===----------------------------------------------------------------------===//
279 class FSHIFT16<bits<5> op, bits<2> _f, dag outs, dag ins, string asmstr,
280 list<dag> pattern, InstrItinClass itin>:
281 MipsInst16<outs, ins, asmstr, pattern, itin, FrmSHIFT16>
297 //===----------------------------------------------------------------------===//
298 // Format i8 instruction class in Mips : <|opcode|funct|imm8>
299 //===----------------------------------------------------------------------===//
301 class FI816<bits<5> op, bits<3> _func, dag outs, dag ins, string asmstr,
302 list<dag> pattern, InstrItinClass itin>:
303 MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_TYPE16>
311 let Inst{10-8} = func;
312 let Inst{7-0} = imm8;
315 //===----------------------------------------------------------------------===//
316 // Format i8_MOVR32 instruction class in Mips : <|opcode|func|ry|r32>
317 //===----------------------------------------------------------------------===//
319 class FI8_MOVR3216<bits<5> op, bits<3> _func, dag outs, dag ins, string asmstr,
320 list<dag> pattern, InstrItinClass itin>:
321 MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_MOVR3216>
331 let Inst{10-8} = func;
339 //===----------------------------------------------------------------------===//
340 // Format i8_MOV32R instruction class in Mips : <|opcode|func|ry|r32>
341 //===----------------------------------------------------------------------===//
343 class FI8_MOV32R16<bits<5> op, bits<3> _func, dag outs, dag ins, string asmstr,
344 list<dag> pattern, InstrItinClass itin>:
345 MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_MOV32R16>
356 let Inst{10-8} = func;
357 let Inst{7-5} = r32{2-0};
358 let Inst{4-3} = r32{4-3};
363 //===----------------------------------------------------------------------===//
364 // Format i8_SVRS instruction class in Mips :
365 // <|opcode|svrs|s|ra|s0|s1|framesize>
366 //===----------------------------------------------------------------------===//
368 class FI8_SVRS16<bits<5> op, bits<3> _SVRS, dag outs, dag ins, string asmstr,
369 list<dag> pattern, InstrItinClass itin>:
370 MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_SVRS16>
382 let Inst{10-8} = SVRS;
387 let Inst{3-0} = framesize;
391 //===----------------------------------------------------------------------===//
392 // Format JAL instruction class in Mips16 :
393 // <|opcode|svrs|s|ra|s0|s1|framesize>
394 //===----------------------------------------------------------------------===//
396 class FJAL16<bits<5> op, bits<1> _X, dag outs, dag ins, string asmstr,
397 list<dag> pattern, InstrItinClass itin>:
398 MipsInst16_32<outs, ins, asmstr, pattern, itin, FrmJAL16>
406 let Inst{31-27} = 0b00011;
408 let Inst{25-21} = imm26{20-16};
409 let Inst{20-16} = imm26{25-21};
410 let Inst{15-0} = imm26{15-0};
415 //===----------------------------------------------------------------------===//
416 // Format EXT-I instruction class in Mips16 :
417 // <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
418 //===----------------------------------------------------------------------===//
420 class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,
421 list<dag> pattern, InstrItinClass itin>:
422 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_I16>
429 let Inst{26-21} = imm16{10-5};
430 let Inst{20-16} = imm16{15-11};
431 let Inst{15-11} = eop;
433 let Inst{4-0} = imm16{4-0};
442 //===----------------------------------------------------------------------===//
443 // Format ASMACRO instruction class in Mips16 :
444 // <EXTEND|select|p4|p3|RRR|p2|p1|p0>
445 //===----------------------------------------------------------------------===//
447 class FASMACRO16<bits<5> op, dag outs, dag ins, string asmstr,
448 list<dag> pattern, InstrItinClass itin>:
449 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
461 let Inst{26-24} = select;
462 let Inst{23-21} = p4;
463 let Inst{20-16} = p3;
464 let Inst{15-11} = RRR;
472 //===----------------------------------------------------------------------===//
473 // Format EXT-RI instruction class in Mips16 :
474 // <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
475 //===----------------------------------------------------------------------===//
477 class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,
478 list<dag> pattern, InstrItinClass itin>:
479 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
488 let Inst{26-21} = imm16{10-5};
489 let Inst{20-16} = imm16{15-11};
490 let Inst{15-11} = op;
493 let Inst{4-0} = imm16{4-0};
497 //===----------------------------------------------------------------------===//
498 // Format EXT-RRI instruction class in Mips16 :
499 // <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
500 //===----------------------------------------------------------------------===//
502 class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr,
503 list<dag> pattern, InstrItinClass itin>:
504 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
512 let Inst{26-21} = imm16{10-5};
513 let Inst{20-16} = imm16{15-11};
514 let Inst{15-11} = _op;
517 let Inst{4-0} = imm16{4-0};
521 //===----------------------------------------------------------------------===//
522 // Format EXT-RRI-A instruction class in Mips16 :
523 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
524 //===----------------------------------------------------------------------===//
526 class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
527 list<dag> pattern, InstrItinClass itin>:
528 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
538 let Inst{26-20} = imm15{10-4};
539 let Inst{19-16} = imm15{14-11};
540 let Inst{15-11} = 0b01000;
544 let Inst{3-0} = imm15{3-0};
548 //===----------------------------------------------------------------------===//
549 // Format EXT-SHIFT instruction class in Mips16 :
550 // <|EXTEND|sa 4:0|s5|0|SHIFT|rx|ry|0|f>
551 //===----------------------------------------------------------------------===//
553 class FEXT_SHIFT16<bits<5> op, bits<2> _f, dag outs, dag ins, string asmstr,
554 list<dag> pattern, InstrItinClass itin>:
555 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
565 let Inst{26-22} = sa6{4-0};
566 let Inst{21} = sa6{5};
568 let Inst{15-11} = 0b00110;
576 //===----------------------------------------------------------------------===//
577 // Format EXT-I8 instruction class in Mips16 :
578 // <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
579 //===----------------------------------------------------------------------===//
581 class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,
582 list<dag> pattern, InstrItinClass itin>:
583 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
592 let Inst{26-21} = imm16{10-5};
593 let Inst{20-16} = imm16{15-11};
594 let Inst{15-11} = I8;
595 let Inst{10-8} = funct;
597 let Inst{4-0} = imm16{4-0};
601 //===----------------------------------------------------------------------===//
602 // Format EXT-I8_SVRS instruction class in Mips16 :
603 // <|EXTEND|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0>
604 //===----------------------------------------------------------------------===//
606 class FEXT_I8_SVRS16<dag outs, dag ins, string asmstr,
607 list<dag> pattern, InstrItinClass itin>:
608 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
622 let Inst{26-24} = xsregs;
623 let Inst{23-20} = framesize{7-4};
625 let Inst{18-16} = aregs;
626 let Inst{15-11} = I8;
627 let Inst{10-8} = SVRS;
632 let Inst{3-0} = framesize{3-0};