1 //===- Mips16InstrFormats.td - Mips Instruction Formats ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // funct or f Function field
17 // immediate 4-,5-,8- or 11-bit immediate, branch displacement, or
18 // or imm address displacement
20 // op 5-bit major operation code
22 // rx 3-bit source or destination register
24 // ry 3-bit source or destination register
26 // rz 3-bit source or destination register
28 // sa 3- or 5-bit shift amount
30 //===----------------------------------------------------------------------===//
32 // Format specifies the encoding used by the instruction. This is part of the
33 // ad-hoc solution used to emit machine instruction encodings by our machine
36 class Format16<bits<5> val> {
40 def Pseudo16 : Format16<0>;
41 def FrmI16 : Format16<1>;
42 def FrmRI16 : Format16<2>;
43 def FrmRR16 : Format16<3>;
44 def FrmRRI16 : Format16<4>;
45 def FrmRRR16 : Format16<5>;
46 def FrmRRI_A16 : Format16<6>;
47 def FrmSHIFT16 : Format16<7>;
48 def FrmI8_TYPE16 : Format16<8>;
49 def FrmI8_MOVR3216 : Format16<9>;
50 def FrmI8_MOV32R16 : Format16<10>;
51 def FrmI8_SVRS16 : Format16<11>;
52 def FrmJAL16 : Format16<12>;
53 def FrmJALX16 : Format16<13>;
54 def FrmEXT_I16 : Format16<14>;
55 def FrmASMACRO16 : Format16<15>;
56 def FrmEXT_RI16 : Format16<16>;
57 def FrmEXT_RRI16 : Format16<17>;
58 def FrmEXT_RRI_A16 : Format16<18>;
59 def FrmEXT_SHIFT16 : Format16<19>;
60 def FrmEXT_I816 : Format16<20>;
61 def FrmEXT_I8_SVRS16 : Format16<21>;
62 def FrmOther16 : Format16<22>; // Instruction w/ a custom format
64 // Base class for Mips 16 Format
65 // This class does not depend on the instruction size
67 class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
68 InstrItinClass itin, Format16 f>: Instruction
72 let Namespace = "Mips";
74 let OutOperandList = outs;
75 let InOperandList = ins;
77 let AsmString = asmstr;
78 let Pattern = pattern;
82 // Attributes specific to Mips instructions...
84 bits<5> FormBits = Form.Value;
86 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
87 let TSFlags{4-0} = FormBits;
89 let Predicates = [InMips16Mode];
93 // Generic Mips 16 Format
95 class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
96 InstrItinClass itin, Format16 f>:
97 MipsInst16_Base<outs, ins, asmstr, pattern, itin, f>
102 // Top 5 bits are the 'opcode' field
103 let Inst{15-11} = Opcode;
107 // For 32 bit extended instruction forms.
109 class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
110 InstrItinClass itin, Format16 f>:
111 MipsInst16_Base<outs, ins, asmstr, pattern, itin, f>
117 class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
118 InstrItinClass itin, Format16 f>:
119 MipsInst16_32<outs, ins, asmstr, pattern, itin, f>
121 let Inst{31-27} = 0b11110;
126 // Mips Pseudo Instructions Format
127 class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
128 MipsInst16<outs, ins, asmstr, pattern, IIPseudo, Pseudo16> {
129 let isCodeGenOnly = 1;
134 //===----------------------------------------------------------------------===//
135 // Format I instruction class in Mips : <|opcode|imm11|>
136 //===----------------------------------------------------------------------===//
138 class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
139 InstrItinClass itin>:
140 MipsInst16<outs, ins, asmstr, pattern, itin, FrmI16>
146 let Inst{10-0} = imm11;
149 //===----------------------------------------------------------------------===//
150 // Format RI instruction class in Mips : <|opcode|rx|imm8|>
151 //===----------------------------------------------------------------------===//
153 class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
154 list<dag> pattern, InstrItinClass itin>:
155 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRI16>
163 let Inst{7-0} = imm8;
166 //===----------------------------------------------------------------------===//
167 // Format RR instruction class in Mips : <|opcode|rx|ry|funct|>
168 //===----------------------------------------------------------------------===//
170 class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
171 list<dag> pattern, InstrItinClass itin>:
172 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
178 let Opcode = 0b11101;
183 let Inst{4-0} = funct;
187 // For conversion functions.
189 class FRR_SF16<bits<5> _funct, bits<3> _subfunct, dag outs, dag ins,
190 string asmstr, list<dag> pattern, InstrItinClass itin>:
191 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
197 let Opcode = 0b11101; // RR
199 let subfunct = _subfunct;
202 let Inst{7-5} = subfunct;
203 let Inst{4-0} = funct;
207 // just used for breakpoint (hardware and software) instructions.
209 class FC16<bits<5> _funct, dag outs, dag ins, string asmstr,
210 list<dag> pattern, InstrItinClass itin>:
211 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
213 bits<6> _code; // code is a keyword in tablegen
216 let Opcode = 0b11101; // RR
219 let Inst{10-5} = _code;
220 let Inst{4-0} = funct;
224 // J(AL)R(C) subformat
226 class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a,
227 dag outs, dag ins, string asmstr,
228 list<dag> pattern, InstrItinClass itin>:
229 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
240 let Opcode = 0b11101;
249 //===----------------------------------------------------------------------===//
250 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
251 //===----------------------------------------------------------------------===//
253 class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,
254 list<dag> pattern, InstrItinClass itin>:
255 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRI16>
266 let Inst{4-0} = imm5;
269 //===----------------------------------------------------------------------===//
270 // Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|>
271 //===----------------------------------------------------------------------===//
273 class FRRR16<bits<2> _f, dag outs, dag ins, string asmstr,
274 list<dag> pattern, InstrItinClass itin>:
275 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRR16>
282 let Opcode = 0b11100;
291 //===----------------------------------------------------------------------===//
292 // Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
293 //===----------------------------------------------------------------------===//
295 class FRRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
296 list<dag> pattern, InstrItinClass itin>:
297 MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRI_A16>
304 let Opcode = 0b01000;
310 let Inst{3-0} = imm4;
313 //===----------------------------------------------------------------------===//
314 // Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|>
315 //===----------------------------------------------------------------------===//
317 class FSHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
318 list<dag> pattern, InstrItinClass itin>:
319 MipsInst16<outs, ins, asmstr, pattern, itin, FrmSHIFT16>
326 let Opcode = 0b00110;
335 //===----------------------------------------------------------------------===//
336 // Format i8 instruction class in Mips : <|opcode|funct|imm8>
337 //===----------------------------------------------------------------------===//
339 class FI816<bits<3> _func, dag outs, dag ins, string asmstr,
340 list<dag> pattern, InstrItinClass itin>:
341 MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_TYPE16>
346 let Opcode = 0b01100;
349 let Inst{10-8} = func;
350 let Inst{7-0} = imm8;
353 //===----------------------------------------------------------------------===//
354 // Format i8_MOVR32 instruction class in Mips : <|opcode|func|ry|r32>
355 //===----------------------------------------------------------------------===//
357 class FI8_MOVR3216<dag outs, dag ins, string asmstr,
358 list<dag> pattern, InstrItinClass itin>:
359 MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_MOVR3216>
365 let Opcode = 0b01100;
367 let Inst{10-8} = 0b111;
375 //===----------------------------------------------------------------------===//
376 // Format i8_MOV32R instruction class in Mips : <|opcode|func|r32|rz>
377 //===----------------------------------------------------------------------===//
379 class FI8_MOV32R16<dag outs, dag ins, string asmstr,
380 list<dag> pattern, InstrItinClass itin>:
381 MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_MOV32R16>
389 let Opcode = 0b01100;
391 let Inst{10-8} = 0b101;
392 let Inst{7-5} = r32{2-0};
393 let Inst{4-3} = r32{4-3};
398 //===----------------------------------------------------------------------===//
399 // Format i8_SVRS instruction class in Mips :
400 // <|opcode|svrs|s|ra|s0|s1|framesize>
401 //===----------------------------------------------------------------------===//
403 class FI8_SVRS16<bits<1> _s, dag outs, dag ins, string asmstr,
404 list<dag> pattern, InstrItinClass itin>:
405 MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_SVRS16>
411 bits<4> framesize = 0;
414 let Opcode = 0b01100;
416 let Inst{10-8} = 0b100;
421 let Inst{3-0} = framesize;
425 //===----------------------------------------------------------------------===//
426 // Format JAL instruction class in Mips16 :
427 // <|opcode|svrs|s|ra|s0|s1|framesize>
428 //===----------------------------------------------------------------------===//
430 class FJAL16<bits<1> _X, dag outs, dag ins, string asmstr,
431 list<dag> pattern, InstrItinClass itin>:
432 MipsInst16_32<outs, ins, asmstr, pattern, itin, FrmJAL16>
440 let Inst{31-27} = 0b00011;
442 let Inst{25-21} = imm26{20-16};
443 let Inst{20-16} = imm26{25-21};
444 let Inst{15-0} = imm26{15-0};
448 //===----------------------------------------------------------------------===//
449 // Format EXT-I instruction class in Mips16 :
450 // <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
451 //===----------------------------------------------------------------------===//
453 class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,
454 list<dag> pattern, InstrItinClass itin>:
455 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_I16>
462 let Inst{26-21} = imm16{10-5};
463 let Inst{20-16} = imm16{15-11};
464 let Inst{15-11} = eop;
466 let Inst{4-0} = imm16{4-0};
470 //===----------------------------------------------------------------------===//
471 // Format ASMACRO instruction class in Mips16 :
472 // <EXTEND|select|p4|p3|RRR|p2|p1|p0>
473 //===----------------------------------------------------------------------===//
475 class FASMACRO16<dag outs, dag ins, string asmstr,
476 list<dag> pattern, InstrItinClass itin>:
477 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmASMACRO16>
482 bits<5> RRR = 0b11100;
488 let Inst{26-24} = select;
489 let Inst{23-21} = p4;
490 let Inst{20-16} = p3;
491 let Inst{15-11} = RRR;
499 //===----------------------------------------------------------------------===//
500 // Format EXT-RI instruction class in Mips16 :
501 // <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
502 //===----------------------------------------------------------------------===//
504 class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,
505 list<dag> pattern, InstrItinClass itin>:
506 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_RI16>
514 let Inst{26-21} = imm16{10-5};
515 let Inst{20-16} = imm16{15-11};
516 let Inst{15-11} = op;
519 let Inst{4-0} = imm16{4-0};
523 //===----------------------------------------------------------------------===//
524 // Format EXT-RRI instruction class in Mips16 :
525 // <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
526 //===----------------------------------------------------------------------===//
528 class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr,
529 list<dag> pattern, InstrItinClass itin>:
530 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_RRI16>
537 let Inst{26-21} = imm16{10-5};
538 let Inst{20-16} = imm16{15-11};
539 let Inst{15-11} = _op;
542 let Inst{4-0} = imm16{4-0};
546 //===----------------------------------------------------------------------===//
547 // Format EXT-RRI-A instruction class in Mips16 :
548 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
549 //===----------------------------------------------------------------------===//
551 class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
552 list<dag> pattern, InstrItinClass itin>:
553 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_RRI_A16>
562 let Inst{26-20} = imm15{10-4};
563 let Inst{19-16} = imm15{14-11};
564 let Inst{15-11} = 0b01000;
568 let Inst{3-0} = imm15{3-0};
572 //===----------------------------------------------------------------------===//
573 // Format EXT-SHIFT instruction class in Mips16 :
574 // <|EXTEND|sa 4:0|s5|0|SHIFT|rx|ry|0|f>
575 //===----------------------------------------------------------------------===//
577 class FEXT_SHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
578 list<dag> pattern, InstrItinClass itin>:
579 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_SHIFT16>
588 let Inst{26-22} = sa6{4-0};
589 let Inst{21} = sa6{5};
591 let Inst{15-11} = 0b00110;
599 //===----------------------------------------------------------------------===//
600 // Format EXT-I8 instruction class in Mips16 :
601 // <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
602 //===----------------------------------------------------------------------===//
604 class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,
605 list<dag> pattern, InstrItinClass itin>:
606 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_I816>
615 let Inst{26-21} = imm16{10-5};
616 let Inst{20-16} = imm16{15-11};
617 let Inst{15-11} = I8;
618 let Inst{10-8} = funct;
620 let Inst{4-0} = imm16{4-0};
624 //===----------------------------------------------------------------------===//
625 // Format EXT-I8_SVRS instruction class in Mips16 :
626 // <|EXTEND|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0>
627 //===----------------------------------------------------------------------===//
629 class FEXT_I8_SVRS16<bits<1> s_, dag outs, dag ins, string asmstr,
630 list<dag> pattern, InstrItinClass itin>:
631 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmI8_SVRS16>
634 bits<8> framesize =0;
636 bits<5> I8 = 0b01100;
637 bits<3> SVRS = 0b100;
645 let Inst{26-24} = xsregs;
646 let Inst{23-20} = framesize{7-4};
648 let Inst{18-16} = aregs;
649 let Inst{15-11} = I8;
650 let Inst{10-8} = SVRS;
655 let Inst{3-0} = framesize{3-0};