1 //===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips16 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Mips16InstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/RegisterScavenging.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
30 static cl::opt<bool> NeverUseSaveRestore(
31 "mips16-never-use-save-restore",
33 cl::desc("For testing ability to adjust stack pointer "
34 "without save/restore instruction"),
38 Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
39 : MipsInstrInfo(tm, Mips::BimmX16),
40 RI(*tm.getSubtargetImpl(), *this) {}
42 const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
46 /// isLoadFromStackSlot - If the specified machine instruction is a direct
47 /// load from a stack slot, return the virtual or physical register number of
48 /// the destination along with the FrameIndex of the loaded stack slot. If
49 /// not, return 0. This predicate must return 0 if the instruction has
50 /// any side effects other than loading from the stack slot.
51 unsigned Mips16InstrInfo::
52 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
57 /// isStoreToStackSlot - If the specified machine instruction is a direct
58 /// store to a stack slot, return the virtual or physical register number of
59 /// the source reg along with the FrameIndex of the loaded stack slot. If
60 /// not, return 0. This predicate must return 0 if the instruction has
61 /// any side effects other than storing to the stack slot.
62 unsigned Mips16InstrInfo::
63 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
68 void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator I, DebugLoc DL,
70 unsigned DestReg, unsigned SrcReg,
74 if (Mips::CPU16RegsRegClass.contains(DestReg) &&
75 Mips::CPURegsRegClass.contains(SrcReg))
76 Opc = Mips::MoveR3216;
77 else if (Mips::CPURegsRegClass.contains(DestReg) &&
78 Mips::CPU16RegsRegClass.contains(SrcReg))
79 Opc = Mips::Move32R16;
80 else if ((SrcReg == Mips::HI) &&
81 (Mips::CPU16RegsRegClass.contains(DestReg)))
82 Opc = Mips::Mfhi16, SrcReg = 0;
84 else if ((SrcReg == Mips::LO) &&
85 (Mips::CPU16RegsRegClass.contains(DestReg)))
86 Opc = Mips::Mflo16, SrcReg = 0;
89 assert(Opc && "Cannot copy registers");
91 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
94 MIB.addReg(DestReg, RegState::Define);
97 MIB.addReg(SrcReg, getKillRegState(KillSrc));
100 void Mips16InstrInfo::
101 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
102 unsigned SrcReg, bool isKill, int FI,
103 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
104 int64_t Offset) const {
106 if (I != MBB.end()) DL = I->getDebugLoc();
107 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
109 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
110 Opc = Mips::SwRxSpImmX16;
111 assert(Opc && "Register class not handled!");
112 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
113 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
116 void Mips16InstrInfo::
117 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
118 unsigned DestReg, int FI, const TargetRegisterClass *RC,
119 const TargetRegisterInfo *TRI, int64_t Offset) const {
121 if (I != MBB.end()) DL = I->getDebugLoc();
122 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
125 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
126 Opc = Mips::LwRxSpImmX16;
127 assert(Opc && "Register class not handled!");
128 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
132 bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
133 MachineBasicBlock &MBB = *MI->getParent();
134 switch(MI->getDesc().getOpcode()) {
138 ExpandRetRA16(MBB, MI, Mips::JrcRa16);
146 /// GetOppositeBranchOpc - Return the inverse of the specified
147 /// opcode, e.g. turning BEQ to BNE.
148 unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
150 default: llvm_unreachable("Illegal opcode!");
151 case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
152 case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
153 case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
154 case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
155 case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
156 case Mips::BtnezX16: return Mips::BteqzX16;
157 case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
158 case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
159 case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
160 case Mips::BteqzX16: return Mips::BtnezX16;
161 case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
162 case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
163 case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
164 case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
165 case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
166 case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
168 assert(false && "Implement this function.");
172 // Adjust SP by FrameSize bytes. Save RA, S0, S1
173 void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
174 MachineBasicBlock &MBB,
175 MachineBasicBlock::iterator I) const {
176 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
177 if (!NeverUseSaveRestore) {
178 if (isUInt<11>(FrameSize))
179 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
181 int Base = 2040; // should create template function like isUInt that
182 // returns largest possible n bit unsigned integer
183 int64_t Remainder = FrameSize - Base;
184 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
185 if (isInt<16>(-Remainder))
186 BuildAddiuSpImm(MBB, I, -Remainder);
188 adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
198 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
200 MIB1.addReg(Mips::SP);
202 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
204 MIB2.addReg(Mips::SP);
206 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
208 MIB3.addReg(Mips::SP);
210 adjustStackPtrBig(SP, -FrameSize, MBB, I, Mips::V0, Mips::V1);
214 // Adjust SP by FrameSize bytes. Restore RA, S0, S1
215 void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
216 MachineBasicBlock &MBB,
217 MachineBasicBlock::iterator I) const {
218 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
219 if (!NeverUseSaveRestore) {
220 if (isUInt<11>(FrameSize))
221 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
223 int Base = 2040; // should create template function like isUInt that
224 // returns largest possible n bit unsigned integer
225 int64_t Remainder = FrameSize - Base;
226 if (isInt<16>(Remainder))
227 BuildAddiuSpImm(MBB, I, Remainder);
229 adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
230 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
234 adjustStackPtrBig(SP, FrameSize, MBB, I, Mips::A0, Mips::A1);
238 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
240 MIB1.addReg(Mips::SP);
242 MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
244 MIB0.addReg(Mips::A0);
245 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
247 MIB2.addReg(Mips::SP);
249 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
251 MIB3.addReg(Mips::SP);
257 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
258 // This can only be called at times that we know that there is at least one free
260 // This is clearly safe at prologue and epilogue.
262 void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
263 MachineBasicBlock &MBB,
264 MachineBasicBlock::iterator I,
265 unsigned Reg1, unsigned Reg2) const {
266 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
267 // MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
268 // unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
269 // unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
273 // add reg1, reg1, reg2
277 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
279 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
280 MIB2.addReg(Mips::SP, RegState::Kill);
281 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
283 MIB3.addReg(Reg2, RegState::Kill);
284 MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
286 MIB4.addReg(Reg1, RegState::Kill);
289 void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
290 MachineBasicBlock &MBB,
291 MachineBasicBlock::iterator I) const {
292 assert(false && "adjust stack pointer amount exceeded");
295 /// Adjust SP by Amount bytes.
296 void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
297 MachineBasicBlock &MBB,
298 MachineBasicBlock::iterator I) const {
299 if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16>
300 BuildAddiuSpImm(MBB, I, Amount);
302 adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
305 /// This function generates the sequence of instructions needed to get the
306 /// result of adding register REG and immediate IMM.
308 Mips16InstrInfo::loadImmediate(unsigned FrameReg,
309 int64_t Imm, MachineBasicBlock &MBB,
310 MachineBasicBlock::iterator II, DebugLoc DL,
311 unsigned &NewImm) const {
313 // given original instruction is:
314 // Instr rx, T[offset] where offset is too big.
316 // lo = offset & 0xFFFF
317 // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
319 // let T = temporary register
325 int32_t lo = Imm & 0xFFFF;
326 int32_t hi = ((Imm >> 16) + (lo >> 15)) & 0xFFFF;
330 rs.enterBasicBlock(&MBB);
333 // we use T0 for the first register, if we need to save something away.
334 // we use T1 for the second register, if we need to save something away.
336 unsigned FirstRegSaved =0, SecondRegSaved=0;
337 unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
339 Reg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
341 FirstRegSaved = Reg = Mips::V0;
342 FirstRegSavedTo = Mips::T0;
343 copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
347 BuildMI(MBB, II, DL, get(Mips::LiRxImmX16), Reg).addImm(hi);
348 BuildMI(MBB, II, DL, get(Mips::SllX16), Reg).addReg(Reg).
350 if (FrameReg == Mips::SP) {
351 SpReg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
353 if (Reg != Mips::V1) {
354 SecondRegSaved = SpReg = Mips::V1;
355 SecondRegSavedTo = Mips::T1;
358 SecondRegSaved = SpReg = Mips::V0;
359 SecondRegSavedTo = Mips::T0;
361 copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
366 copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
367 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg)
371 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
372 .addReg(Reg, RegState::Kill);
373 if (FirstRegSaved || SecondRegSaved) {
376 copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
378 copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
383 unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
384 return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
385 Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
386 Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
387 Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
388 Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
389 Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
390 Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
391 Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
392 Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
395 void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
396 MachineBasicBlock::iterator I,
397 unsigned Opc) const {
398 BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
402 const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
403 if (validSpImm8(Imm))
404 return get(Mips::AddiuSpImm16);
406 return get(Mips::AddiuSpImmX16);
409 void Mips16InstrInfo::BuildAddiuSpImm
410 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
411 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
412 BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
415 const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
416 return new Mips16InstrInfo(TM);