2 //===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
4 // The LLVM Compiler Infrastructure
6 // This file is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the Mips16 implementation of the TargetInstrInfo class.
13 //===----------------------------------------------------------------------===//
14 #include "Mips16InstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/RegisterScavenging.h"
23 #include "llvm/MC/MCAsmInfo.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
33 Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
34 : MipsInstrInfo(tm, Mips::Bimm16),
35 RI(*tm.getSubtargetImpl()) {}
37 const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
41 /// isLoadFromStackSlot - If the specified machine instruction is a direct
42 /// load from a stack slot, return the virtual or physical register number of
43 /// the destination along with the FrameIndex of the loaded stack slot. If
44 /// not, return 0. This predicate must return 0 if the instruction has
45 /// any side effects other than loading from the stack slot.
46 unsigned Mips16InstrInfo::
47 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
52 /// isStoreToStackSlot - If the specified machine instruction is a direct
53 /// store to a stack slot, return the virtual or physical register number of
54 /// the source reg along with the FrameIndex of the loaded stack slot. If
55 /// not, return 0. This predicate must return 0 if the instruction has
56 /// any side effects other than storing to the stack slot.
57 unsigned Mips16InstrInfo::
58 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
63 void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
64 MachineBasicBlock::iterator I, DebugLoc DL,
65 unsigned DestReg, unsigned SrcReg,
69 if (Mips::CPU16RegsRegClass.contains(DestReg) &&
70 Mips::GPR32RegClass.contains(SrcReg))
71 Opc = Mips::MoveR3216;
72 else if (Mips::GPR32RegClass.contains(DestReg) &&
73 Mips::CPU16RegsRegClass.contains(SrcReg))
74 Opc = Mips::Move32R16;
75 else if ((SrcReg == Mips::HI0) &&
76 (Mips::CPU16RegsRegClass.contains(DestReg)))
77 Opc = Mips::Mfhi16, SrcReg = 0;
79 else if ((SrcReg == Mips::LO0) &&
80 (Mips::CPU16RegsRegClass.contains(DestReg)))
81 Opc = Mips::Mflo16, SrcReg = 0;
84 assert(Opc && "Cannot copy registers");
86 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
89 MIB.addReg(DestReg, RegState::Define);
92 MIB.addReg(SrcReg, getKillRegState(KillSrc));
95 void Mips16InstrInfo::
96 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
97 unsigned SrcReg, bool isKill, int FI,
98 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
99 int64_t Offset) const {
101 if (I != MBB.end()) DL = I->getDebugLoc();
102 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
104 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
105 Opc = Mips::SwRxSpImmX16;
106 assert(Opc && "Register class not handled!");
107 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
108 addFrameIndex(FI).addImm(Offset)
112 void Mips16InstrInfo::
113 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
114 unsigned DestReg, int FI, const TargetRegisterClass *RC,
115 const TargetRegisterInfo *TRI, int64_t Offset) const {
117 if (I != MBB.end()) DL = I->getDebugLoc();
118 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
121 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
122 Opc = Mips::LwRxSpImmX16;
123 assert(Opc && "Register class not handled!");
124 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
128 bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
129 MachineBasicBlock &MBB = *MI->getParent();
130 switch(MI->getDesc().getOpcode()) {
134 ExpandRetRA16(MBB, MI, Mips::JrcRa16);
142 /// GetOppositeBranchOpc - Return the inverse of the specified
143 /// opcode, e.g. turning BEQ to BNE.
144 unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {
146 default: llvm_unreachable("Illegal opcode!");
147 case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
148 case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
149 case Mips::BeqzRxImm16: return Mips::BnezRxImm16;
150 case Mips::BnezRxImm16: return Mips::BeqzRxImm16;
151 case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
152 case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
153 case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
154 case Mips::Btnez16: return Mips::Bteqz16;
155 case Mips::BtnezX16: return Mips::BteqzX16;
156 case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
157 case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
158 case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
159 case Mips::Bteqz16: return Mips::Btnez16;
160 case Mips::BteqzX16: return Mips::BtnezX16;
161 case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
162 case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
163 case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
164 case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
165 case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
166 case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
168 assert(false && "Implement this function.");
172 static void addSaveRestoreRegs(MachineInstrBuilder &MIB,
173 const std::vector<CalleeSavedInfo> &CSI, unsigned Flags=0) {
174 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
175 // Add the callee-saved register as live-in. Do not add if the register is
176 // RA and return address is taken, because it has already been added in
177 // method MipsTargetLowering::LowerRETURNADDR.
178 // It's killed at the spill, unless the register is RA and return address
180 unsigned Reg = CSI[e-i-1].getReg();
185 MIB.addReg(Reg, Flags);
190 llvm_unreachable("unexpected mips16 callee saved register");
195 // Adjust SP by FrameSize bytes. Save RA, S0, S1
196 void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
197 MachineBasicBlock &MBB,
198 MachineBasicBlock::iterator I) const {
199 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
200 MachineFunction &MF = *MBB.getParent();
201 MachineFrameInfo *MFI = MF.getFrameInfo();
202 const BitVector Reserved = RI.getReservedRegs(MF);
203 bool SaveS2 = Reserved[Mips::S2];
204 MachineInstrBuilder MIB;
205 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16;
206 MIB = BuildMI(MBB, I, DL, get(Opc));
207 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
208 addSaveRestoreRegs(MIB, CSI);
210 MIB.addReg(Mips::S2);
211 if (isUInt<11>(FrameSize))
212 MIB.addImm(FrameSize);
214 int Base = 2040; // should create template function like isUInt that
215 // returns largest possible n bit unsigned integer
216 int64_t Remainder = FrameSize - Base;
218 if (isInt<16>(-Remainder))
219 BuildAddiuSpImm(MBB, I, -Remainder);
221 adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
225 // Adjust SP by FrameSize bytes. Restore RA, S0, S1
226 void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
227 MachineBasicBlock &MBB,
228 MachineBasicBlock::iterator I) const {
229 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
230 MachineFunction *MF = MBB.getParent();
231 MachineFrameInfo *MFI = MF->getFrameInfo();
232 const BitVector Reserved = RI.getReservedRegs(*MF);
233 bool SaveS2 = Reserved[Mips::S2];
234 MachineInstrBuilder MIB;
235 unsigned Opc = ((FrameSize <= 128) && !SaveS2)?
236 Mips::Restore16:Mips::RestoreX16;
238 if (!isUInt<11>(FrameSize)) {
239 unsigned Base = 2040;
240 int64_t Remainder = FrameSize - Base;
241 FrameSize = Base; // should create template function like isUInt that
242 // returns largest possible n bit unsigned integer
244 if (isInt<16>(Remainder))
245 BuildAddiuSpImm(MBB, I, Remainder);
247 adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
249 MIB = BuildMI(MBB, I, DL, get(Opc));
250 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
251 addSaveRestoreRegs(MIB, CSI, RegState::Define);
253 MIB.addReg(Mips::S2, RegState::Define);
254 MIB.addImm(FrameSize);
257 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
258 // This can only be called at times that we know that there is at least one free
260 // This is clearly safe at prologue and epilogue.
262 void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
263 MachineBasicBlock &MBB,
264 MachineBasicBlock::iterator I,
265 unsigned Reg1, unsigned Reg2) const {
266 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
267 // MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
268 // unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
269 // unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
273 // add reg1, reg1, reg2
277 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
278 MIB1.addImm(Amount).addImm(-1);
279 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
280 MIB2.addReg(Mips::SP, RegState::Kill);
281 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
283 MIB3.addReg(Reg2, RegState::Kill);
284 MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
286 MIB4.addReg(Reg1, RegState::Kill);
289 void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
290 MachineBasicBlock &MBB,
291 MachineBasicBlock::iterator I) const {
292 assert(false && "adjust stack pointer amount exceeded");
295 /// Adjust SP by Amount bytes.
296 void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
297 MachineBasicBlock &MBB,
298 MachineBasicBlock::iterator I) const {
299 if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16>
300 BuildAddiuSpImm(MBB, I, Amount);
302 adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
305 /// This function generates the sequence of instructions needed to get the
306 /// result of adding register REG and immediate IMM.
308 Mips16InstrInfo::loadImmediate(unsigned FrameReg,
309 int64_t Imm, MachineBasicBlock &MBB,
310 MachineBasicBlock::iterator II, DebugLoc DL,
311 unsigned &NewImm) const {
313 // given original instruction is:
314 // Instr rx, T[offset] where offset is too big.
316 // lo = offset & 0xFFFF
317 // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
319 // let T = temporary register
325 int32_t lo = Imm & 0xFFFF;
330 rs.enterBasicBlock(&MBB);
333 // We need to know which registers can be used, in the case where there
334 // are not enough free registers. We exclude all registers that
335 // are used in the instruction that we are helping.
336 // // Consider all allocatable registers in the register class initially
337 BitVector Candidates =
339 (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
340 // Exclude all the registers being used by the instruction.
341 for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
342 MachineOperand &MO = II->getOperand(i);
343 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
344 !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
345 Candidates.reset(MO.getReg());
348 // If the same register was used and defined in an instruction, then
349 // it will not be in the list of candidates.
351 // we need to analyze the instruction that we are helping.
352 // we need to know if it defines register x but register x is not
353 // present as an operand of the instruction. this tells
354 // whether the register is live before the instruction. if it's not
355 // then we don't need to save it in case there are no free registers.
358 for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
359 MachineOperand &MO = II->getOperand(i);
360 if (MO.isReg() && MO.isDef()) {
361 DefReg = MO.getReg();
366 BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass);
368 Available &= Candidates;
370 // we use T0 for the first register, if we need to save something away.
371 // we use T1 for the second register, if we need to save something away.
373 unsigned FirstRegSaved =0, SecondRegSaved=0;
374 unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
377 Reg = Available.find_first();
380 Reg = Candidates.find_first();
381 Candidates.reset(Reg);
384 FirstRegSavedTo = Mips::T0;
385 copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
389 Available.reset(Reg);
390 BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1);
392 if (FrameReg == Mips::SP) {
393 SpReg = Available.find_first();
395 SpReg = Candidates.find_first();
396 // Candidates.reset(SpReg); // not really needed
397 if (DefReg!= SpReg) {
398 SecondRegSaved = SpReg;
399 SecondRegSavedTo = Mips::T1;
402 copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
405 Available.reset(SpReg);
406 copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
407 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
411 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
412 .addReg(Reg, RegState::Kill);
413 if (FirstRegSaved || SecondRegSaved) {
416 copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
418 copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
423 unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
424 return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
425 Opc == Mips::Bimm16 ||
426 Opc == Mips::Bteqz16 || Opc == Mips::Btnez16 ||
427 Opc == Mips::BeqzRxImm16 || Opc == Mips::BnezRxImm16 ||
428 Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
429 Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
430 Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
431 Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
432 Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
433 Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
434 Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
435 Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
438 void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
439 MachineBasicBlock::iterator I,
440 unsigned Opc) const {
441 BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
445 const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
446 if (validSpImm8(Imm))
447 return get(Mips::AddiuSpImm16);
449 return get(Mips::AddiuSpImmX16);
452 void Mips16InstrInfo::BuildAddiuSpImm
453 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
454 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
455 BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
458 const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
459 return new Mips16InstrInfo(TM);
462 bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,
465 case Mips::LbRxRyOffMemX16:
466 case Mips::LbuRxRyOffMemX16:
467 case Mips::LhRxRyOffMemX16:
468 case Mips::LhuRxRyOffMemX16:
469 case Mips::SbRxRyOffMemX16:
470 case Mips::ShRxRyOffMemX16:
471 case Mips::LwRxRyOffMemX16:
472 case Mips::SwRxRyOffMemX16:
473 case Mips::SwRxSpImmX16:
474 case Mips::LwRxSpImmX16:
475 return isInt<16>(Amount);
476 case Mips::AddiuRxRyOffMemX16:
477 if ((Reg == Mips::PC) || (Reg == Mips::SP))
478 return isInt<16>(Amount);
479 return isInt<15>(Amount);
481 llvm_unreachable("unexpected Opcode in validImmediate");
484 /// Measure the specified inline asm to determine an approximation of its
486 /// Comments (which run till the next SeparatorString or newline) do not
487 /// count as an instruction.
488 /// Any other non-whitespace text is considered an instruction, with
489 /// multiple instructions separated by SeparatorString or newlines.
490 /// Variable-length instructions are not handled here; this function
491 /// may be overloaded in the target code to do that.
492 /// We implement the special case of the .space directive taking only an
493 /// integer argument, which is the size in bytes. This is used for creating
494 /// inline code spacing for testing purposes using inline assembly.
496 unsigned Mips16InstrInfo::getInlineAsmLength(const char *Str,
497 const MCAsmInfo &MAI) const {
500 // Count the number of instructions in the asm.
501 bool atInsnStart = true;
503 for (; *Str; ++Str) {
504 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
505 strlen(MAI.getSeparatorString())) == 0)
507 if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
508 if (strncmp(Str, ".space", 6)==0) {
510 Sz = strtol(Str+6, &EStr, 10);
511 while (isspace(*EStr)) ++EStr;
513 DEBUG(dbgs() << "parsed .space " << Sz << '\n');
517 Length += MAI.getMaxInstLength();
520 if (atInsnStart && strncmp(Str, MAI.getCommentString(),
521 strlen(MAI.getCommentString())) == 0)