1 //===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips16 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Mips16InstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/RegisterScavenging.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h"
29 static cl::opt<bool> NeverUseSaveRestore(
30 "mips16-never-use-save-restore",
32 cl::desc("For testing ability to adjust stack pointer "
33 "without save/restore instruction"),
37 Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
38 : MipsInstrInfo(tm, Mips::BimmX16),
39 RI(*tm.getSubtargetImpl(), *this) {}
41 const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
45 /// isLoadFromStackSlot - If the specified machine instruction is a direct
46 /// load from a stack slot, return the virtual or physical register number of
47 /// the destination along with the FrameIndex of the loaded stack slot. If
48 /// not, return 0. This predicate must return 0 if the instruction has
49 /// any side effects other than loading from the stack slot.
50 unsigned Mips16InstrInfo::
51 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
56 /// isStoreToStackSlot - If the specified machine instruction is a direct
57 /// store to a stack slot, return the virtual or physical register number of
58 /// the source reg along with the FrameIndex of the loaded stack slot. If
59 /// not, return 0. This predicate must return 0 if the instruction has
60 /// any side effects other than storing to the stack slot.
61 unsigned Mips16InstrInfo::
62 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
67 void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
68 MachineBasicBlock::iterator I, DebugLoc DL,
69 unsigned DestReg, unsigned SrcReg,
73 if (Mips::CPU16RegsRegClass.contains(DestReg) &&
74 Mips::CPURegsRegClass.contains(SrcReg))
75 Opc = Mips::MoveR3216;
76 else if (Mips::CPURegsRegClass.contains(DestReg) &&
77 Mips::CPU16RegsRegClass.contains(SrcReg))
78 Opc = Mips::Move32R16;
79 else if ((SrcReg == Mips::HI) &&
80 (Mips::CPU16RegsRegClass.contains(DestReg)))
81 Opc = Mips::Mfhi16, SrcReg = 0;
83 else if ((SrcReg == Mips::LO) &&
84 (Mips::CPU16RegsRegClass.contains(DestReg)))
85 Opc = Mips::Mflo16, SrcReg = 0;
88 assert(Opc && "Cannot copy registers");
90 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
93 MIB.addReg(DestReg, RegState::Define);
96 MIB.addReg(SrcReg, getKillRegState(KillSrc));
99 void Mips16InstrInfo::
100 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
101 unsigned SrcReg, bool isKill, int FI,
102 const TargetRegisterClass *RC,
103 const TargetRegisterInfo *TRI) const {
105 if (I != MBB.end()) DL = I->getDebugLoc();
106 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
108 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
109 Opc = Mips::SwRxSpImmX16;
110 assert(Opc && "Register class not handled!");
111 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
112 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
115 void Mips16InstrInfo::
116 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
117 unsigned DestReg, int FI,
118 const TargetRegisterClass *RC,
119 const TargetRegisterInfo *TRI) const {
121 if (I != MBB.end()) DL = I->getDebugLoc();
122 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
125 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
126 Opc = Mips::LwRxSpImmX16;
127 assert(Opc && "Register class not handled!");
128 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
132 bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
133 MachineBasicBlock &MBB = *MI->getParent();
135 switch(MI->getDesc().getOpcode()) {
139 ExpandRetRA16(MBB, MI, Mips::JrcRa16);
147 /// GetOppositeBranchOpc - Return the inverse of the specified
148 /// opcode, e.g. turning BEQ to BNE.
149 unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
151 default: llvm_unreachable("Illegal opcode!");
152 case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
153 case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
154 case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
155 case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
156 case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
157 case Mips::BtnezX16: return Mips::BteqzX16;
158 case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
159 case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
160 case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
161 case Mips::BteqzX16: return Mips::BtnezX16;
162 case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
163 case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
164 case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
165 case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
166 case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
167 case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
169 assert(false && "Implement this function.");
173 // Adjust SP by FrameSize bytes. Save RA, S0, S1
174 void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
175 MachineBasicBlock &MBB,
176 MachineBasicBlock::iterator I) const {
177 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
178 if (!NeverUseSaveRestore) {
179 if (isUInt<11>(FrameSize))
180 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
182 int Base = 2040; // should create template function like isUInt that
183 // returns largest possible n bit unsigned integer
184 int64_t Remainder = FrameSize - Base;
185 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
186 if (isInt<16>(-Remainder))
187 BuildAddiuSpImm(MBB, I, DL, -Remainder);
189 adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
199 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
201 MIB1.addReg(Mips::SP);
203 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
205 MIB2.addReg(Mips::SP);
207 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
209 MIB3.addReg(Mips::SP);
211 adjustStackPtrBig(SP, -FrameSize, MBB, I, Mips::V0, Mips::V1);
215 // Adjust SP by FrameSize bytes. Restore RA, S0, S1
216 void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
217 MachineBasicBlock &MBB,
218 MachineBasicBlock::iterator I) const {
219 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
220 if (!NeverUseSaveRestore) {
221 if (isUInt<11>(FrameSize))
222 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
224 int Base = 2040; // should create template function like isUInt that
225 // returns largest possible n bit unsigned integer
226 int64_t Remainder = FrameSize - Base;
227 if (isInt<16>(Remainder))
228 BuildAddiuSpImm(MBB, I, DL, Remainder);
230 adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
231 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
235 adjustStackPtrBig(SP, FrameSize, MBB, I, Mips::A0, Mips::A1);
239 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
241 MIB1.addReg(Mips::SP);
243 MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
245 MIB0.addReg(Mips::A0);
246 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
248 MIB2.addReg(Mips::SP);
250 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
252 MIB3.addReg(Mips::SP);
258 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
259 // This can only be called at times that we know that there is at least one free
261 // This is clearly safe at prologue and epilogue.
263 void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
264 MachineBasicBlock &MBB,
265 MachineBasicBlock::iterator I,
266 unsigned Reg1, unsigned Reg2) const {
267 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
268 // MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
269 // unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
270 // unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
274 // add reg1, reg1, reg2
278 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
280 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
281 MIB2.addReg(Mips::SP, RegState::Kill);
282 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
284 MIB3.addReg(Reg2, RegState::Kill);
285 MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
287 MIB4.addReg(Reg1, RegState::Kill);
290 void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
291 MachineBasicBlock &MBB,
292 MachineBasicBlock::iterator I) const {
293 assert(false && "adjust stack pointer amount exceeded");
296 /// Adjust SP by Amount bytes.
297 void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
298 MachineBasicBlock &MBB,
299 MachineBasicBlock::iterator I) const {
300 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
301 if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16>
302 BuildAddiuSpImm(MBB, I, DL, Amount);
304 adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
307 /// This function generates the sequence of instructions needed to get the
308 /// result of adding register REG and immediate IMM.
310 Mips16InstrInfo::loadImmediate(unsigned FrameReg,
311 int64_t Imm, MachineBasicBlock &MBB,
312 MachineBasicBlock::iterator II, DebugLoc DL,
313 unsigned &NewImm) const {
315 // given original instruction is:
316 // Instr rx, T[offset] where offset is too big.
318 // lo = offset & 0xFFFF
319 // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
321 // let T = temporary register
327 int32_t lo = Imm & 0xFFFF;
328 int32_t hi = ((Imm >> 16) + (lo >> 15)) & 0xFFFF;
332 rs.enterBasicBlock(&MBB);
335 // we use T0 for the first register, if we need to save something away.
336 // we use T1 for the second register, if we need to save something away.
338 unsigned FirstRegSaved =0, SecondRegSaved=0;
339 unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
341 Reg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
343 FirstRegSaved = Reg = Mips::V0;
344 FirstRegSavedTo = Mips::T0;
345 copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
349 BuildMI(MBB, II, DL, get(Mips::LiRxImmX16), Reg).addImm(hi);
350 BuildMI(MBB, II, DL, get(Mips::SllX16), Reg).addReg(Reg).
352 if (FrameReg == Mips::SP) {
353 SpReg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
355 if (Reg != Mips::V1) {
356 SecondRegSaved = SpReg = Mips::V1;
357 SecondRegSavedTo = Mips::T1;
360 SecondRegSaved = SpReg = Mips::V0;
361 SecondRegSavedTo = Mips::T0;
363 copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
368 copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
369 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg)
373 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
374 .addReg(Reg, RegState::Kill);
375 if (FirstRegSaved || SecondRegSaved) {
378 copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
380 copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
385 unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
386 return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
387 Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
388 Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
389 Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
390 Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
391 Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
392 Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
393 Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
394 Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
397 void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
398 MachineBasicBlock::iterator I,
399 unsigned Opc) const {
400 BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
403 void Mips16InstrInfo::BuildAddiuSpImm(
404 MachineBasicBlock &MBB,
405 MachineBasicBlock::iterator II, DebugLoc DL, int64_t Imm) const {
406 if (validSpImm8(Imm))
407 BuildMI(MBB, II, DL, get(Mips::AddiuSpImm16)).addImm(Imm);
409 BuildMI(MBB, II, DL, get(Mips::AddiuSpImmX16)).addImm(Imm);
412 const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
413 return new Mips16InstrInfo(TM);