1 //===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips16 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Mips16InstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/RegisterScavenging.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
30 static cl::opt<bool> NeverUseSaveRestore(
31 "mips16-never-use-save-restore",
33 cl::desc("For testing ability to adjust stack pointer "
34 "without save/restore instruction"),
38 Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
39 : MipsInstrInfo(tm, Mips::BimmX16),
40 RI(*tm.getSubtargetImpl(), *this) {}
42 const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
46 /// isLoadFromStackSlot - If the specified machine instruction is a direct
47 /// load from a stack slot, return the virtual or physical register number of
48 /// the destination along with the FrameIndex of the loaded stack slot. If
49 /// not, return 0. This predicate must return 0 if the instruction has
50 /// any side effects other than loading from the stack slot.
51 unsigned Mips16InstrInfo::
52 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
57 /// isStoreToStackSlot - If the specified machine instruction is a direct
58 /// store to a stack slot, return the virtual or physical register number of
59 /// the source reg along with the FrameIndex of the loaded stack slot. If
60 /// not, return 0. This predicate must return 0 if the instruction has
61 /// any side effects other than storing to the stack slot.
62 unsigned Mips16InstrInfo::
63 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
68 void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator I, DebugLoc DL,
70 unsigned DestReg, unsigned SrcReg,
74 if (Mips::CPU16RegsRegClass.contains(DestReg) &&
75 Mips::CPURegsRegClass.contains(SrcReg))
76 Opc = Mips::MoveR3216;
77 else if (Mips::CPURegsRegClass.contains(DestReg) &&
78 Mips::CPU16RegsRegClass.contains(SrcReg))
79 Opc = Mips::Move32R16;
80 else if ((SrcReg == Mips::HI) &&
81 (Mips::CPU16RegsRegClass.contains(DestReg)))
82 Opc = Mips::Mfhi16, SrcReg = 0;
84 else if ((SrcReg == Mips::LO) &&
85 (Mips::CPU16RegsRegClass.contains(DestReg)))
86 Opc = Mips::Mflo16, SrcReg = 0;
89 assert(Opc && "Cannot copy registers");
91 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
94 MIB.addReg(DestReg, RegState::Define);
97 MIB.addReg(SrcReg, getKillRegState(KillSrc));
100 void Mips16InstrInfo::
101 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
102 unsigned SrcReg, bool isKill, int FI,
103 const TargetRegisterClass *RC,
104 const TargetRegisterInfo *TRI) const {
106 if (I != MBB.end()) DL = I->getDebugLoc();
107 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
109 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
110 Opc = Mips::SwRxSpImmX16;
111 assert(Opc && "Register class not handled!");
112 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
113 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
116 void Mips16InstrInfo::
117 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
118 unsigned DestReg, int FI,
119 const TargetRegisterClass *RC,
120 const TargetRegisterInfo *TRI) const {
122 if (I != MBB.end()) DL = I->getDebugLoc();
123 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
126 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
127 Opc = Mips::LwRxSpImmX16;
128 assert(Opc && "Register class not handled!");
129 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
133 bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
134 MachineBasicBlock &MBB = *MI->getParent();
136 switch(MI->getDesc().getOpcode()) {
139 case Mips::BteqzT8CmpX16:
140 ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::CmpRxRy16);
142 case Mips::BteqzT8CmpiX16:
143 ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16,
144 Mips::CmpiRxImm16, Mips::CmpiRxImmX16);
146 case Mips::BteqzT8SltX16:
147 ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltRxRy16);
149 case Mips::BteqzT8SltuX16:
150 // TBD: figure out a way to get this or remove the instruction
152 ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltuRxRy16);
154 case Mips::BtnezT8CmpX16:
155 ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16);
157 case Mips::BtnezT8CmpiX16:
158 ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16,
159 Mips::CmpiRxImm16, Mips::CmpiRxImmX16);
161 case Mips::BtnezT8SltX16:
162 ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltRxRy16);
164 case Mips::BtnezT8SltuX16:
165 // TBD: figure out a way to get this or remove the instruction
167 ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltuRxRy16);
170 ExpandRetRA16(MBB, MI, Mips::JrcRa16);
178 /// GetOppositeBranchOpc - Return the inverse of the specified
179 /// opcode, e.g. turning BEQ to BNE.
180 unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
182 default: llvm_unreachable("Illegal opcode!");
183 case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
184 case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
185 case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
186 case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
187 case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
188 case Mips::BtnezX16: return Mips::BteqzX16;
189 case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
190 case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
191 case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
192 case Mips::BteqzX16: return Mips::BtnezX16;
193 case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
194 case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
195 case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
196 case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
197 case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
198 case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
200 assert(false && "Implement this function.");
204 // Adjust SP by FrameSize bytes. Save RA, S0, S1
205 void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
206 MachineBasicBlock &MBB,
207 MachineBasicBlock::iterator I) const {
208 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
209 if (!NeverUseSaveRestore) {
210 if (isUInt<11>(FrameSize))
211 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
213 int Base = 2040; // should create template function like isUInt that
214 // returns largest possible n bit unsigned integer
215 int64_t Remainder = FrameSize - Base;
216 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
217 if (isInt<16>(-Remainder))
218 BuildAddiuSpImm(MBB, I, -Remainder);
220 adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
230 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
232 MIB1.addReg(Mips::SP);
234 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
236 MIB2.addReg(Mips::SP);
238 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
240 MIB3.addReg(Mips::SP);
242 adjustStackPtrBig(SP, -FrameSize, MBB, I, Mips::V0, Mips::V1);
246 // Adjust SP by FrameSize bytes. Restore RA, S0, S1
247 void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
248 MachineBasicBlock &MBB,
249 MachineBasicBlock::iterator I) const {
250 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
251 if (!NeverUseSaveRestore) {
252 if (isUInt<11>(FrameSize))
253 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
255 int Base = 2040; // should create template function like isUInt that
256 // returns largest possible n bit unsigned integer
257 int64_t Remainder = FrameSize - Base;
258 if (isInt<16>(Remainder))
259 BuildAddiuSpImm(MBB, I, Remainder);
261 adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
262 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
266 adjustStackPtrBig(SP, FrameSize, MBB, I, Mips::A0, Mips::A1);
270 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
272 MIB1.addReg(Mips::SP);
274 MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
276 MIB0.addReg(Mips::A0);
277 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
279 MIB2.addReg(Mips::SP);
281 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
283 MIB3.addReg(Mips::SP);
289 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
290 // This can only be called at times that we know that there is at least one free
292 // This is clearly safe at prologue and epilogue.
294 void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
295 MachineBasicBlock &MBB,
296 MachineBasicBlock::iterator I,
297 unsigned Reg1, unsigned Reg2) const {
298 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
299 // MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
300 // unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
301 // unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
305 // add reg1, reg1, reg2
309 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
311 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
312 MIB2.addReg(Mips::SP, RegState::Kill);
313 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
315 MIB3.addReg(Reg2, RegState::Kill);
316 MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
318 MIB4.addReg(Reg1, RegState::Kill);
321 void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
322 MachineBasicBlock &MBB,
323 MachineBasicBlock::iterator I) const {
324 assert(false && "adjust stack pointer amount exceeded");
327 /// Adjust SP by Amount bytes.
328 void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
329 MachineBasicBlock &MBB,
330 MachineBasicBlock::iterator I) const {
331 if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16>
332 BuildAddiuSpImm(MBB, I, Amount);
334 adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
337 /// This function generates the sequence of instructions needed to get the
338 /// result of adding register REG and immediate IMM.
340 Mips16InstrInfo::loadImmediate(unsigned FrameReg,
341 int64_t Imm, MachineBasicBlock &MBB,
342 MachineBasicBlock::iterator II, DebugLoc DL,
343 unsigned &NewImm) const {
345 // given original instruction is:
346 // Instr rx, T[offset] where offset is too big.
348 // lo = offset & 0xFFFF
349 // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
351 // let T = temporary register
357 int32_t lo = Imm & 0xFFFF;
358 int32_t hi = ((Imm >> 16) + (lo >> 15)) & 0xFFFF;
362 rs.enterBasicBlock(&MBB);
365 // we use T0 for the first register, if we need to save something away.
366 // we use T1 for the second register, if we need to save something away.
368 unsigned FirstRegSaved =0, SecondRegSaved=0;
369 unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
371 Reg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
373 FirstRegSaved = Reg = Mips::V0;
374 FirstRegSavedTo = Mips::T0;
375 copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
379 BuildMI(MBB, II, DL, get(Mips::LiRxImmX16), Reg).addImm(hi);
380 BuildMI(MBB, II, DL, get(Mips::SllX16), Reg).addReg(Reg).
382 if (FrameReg == Mips::SP) {
383 SpReg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
385 if (Reg != Mips::V1) {
386 SecondRegSaved = SpReg = Mips::V1;
387 SecondRegSavedTo = Mips::T1;
390 SecondRegSaved = SpReg = Mips::V0;
391 SecondRegSavedTo = Mips::T0;
393 copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
398 copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
399 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg)
403 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
404 .addReg(Reg, RegState::Kill);
405 if (FirstRegSaved || SecondRegSaved) {
408 copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
410 copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
415 unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
416 return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
417 Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
418 Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
419 Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
420 Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
421 Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
422 Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
423 Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
424 Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
427 void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
428 MachineBasicBlock::iterator I,
429 unsigned Opc) const {
430 BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
434 void Mips16InstrInfo::ExpandFEXT_T8I816_ins(
435 MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
436 unsigned BtOpc, unsigned CmpOpc) const {
437 unsigned regX = I->getOperand(0).getReg();
438 unsigned regY = I->getOperand(1).getReg();
439 MachineBasicBlock *target = I->getOperand(2).getMBB();
440 BuildMI(MBB, I, I->getDebugLoc(), get(CmpOpc)).addReg(regX).addReg(regY);
441 BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target);
445 void Mips16InstrInfo::ExpandFEXT_T8I8I16_ins(
446 MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
447 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc) const {
448 unsigned regX = I->getOperand(0).getReg();
449 int64_t imm = I->getOperand(1).getImm();
450 MachineBasicBlock *target = I->getOperand(2).getMBB();
454 else if (isUInt<16>(imm))
457 llvm_unreachable("immediate field not usable");
458 BuildMI(MBB, I, I->getDebugLoc(), get(CmpOpc)).addReg(regX).addImm(imm);
459 BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target);
462 const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
463 if (validSpImm8(Imm))
464 return get(Mips::AddiuSpImm16);
466 return get(Mips::AddiuSpImmX16);
469 void Mips16InstrInfo::BuildAddiuSpImm
470 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
471 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
472 BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
475 const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
476 return new Mips16InstrInfo(TM);