1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
17 def mem16 : Operand<i32> {
18 let PrintMethod = "printMemOperand";
19 let MIOperandInfo = (ops CPU16Regs, simm16);
20 let EncoderMethod = "getMemEncoding";
24 // Compare a register and immediate and place result in CC
27 // EXT-CCRR Instruction format
29 class FEXT_CCRXI16_ins<bits<5> _op, string asmstr,
31 FEXT_RI16<_op, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
32 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), [], itin> {
37 // EXT-I instruction format
39 class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
40 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
41 !strconcat(asmstr, "\t$imm16"),[], itin>;
44 // EXT-I8 instruction format
47 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
48 string asmstr2, InstrItinClass itin>:
49 FEXT_I816<_func, (outs), (ins uimm16:$imm), !strconcat(asmstr, asmstr2),
52 class FEXT_I816_ins<bits<3> _func, string asmstr,
54 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
57 // Assembler formats in alphabetical order.
58 // Natural and pseudos are mixed together.
60 // Compare two registers and place result in CC
63 // CC-RR Instruction format
65 class FCCRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
66 FRR16<f, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
67 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), [], itin> {
72 // EXT-RI instruction format
75 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
77 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
78 !strconcat(asmstr, asmstr2), [], itin>;
80 class FEXT_RI16_ins<bits<5> _op, string asmstr,
82 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
84 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
85 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
87 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
89 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
90 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
92 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
94 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
95 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
96 let Constraints = "$rx_ = $rx";
100 // this has an explicit sp argument that we ignore to work around a problem
102 class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
103 InstrItinClass itin>:
104 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
105 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
108 // EXT-RRI instruction format
111 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
112 InstrItinClass itin>:
113 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
114 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
116 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
117 InstrItinClass itin>:
118 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
119 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
122 // EXT-SHIFT instruction format
124 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
125 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
126 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
131 class FEXT_T8I816_ins<bits<3> _func, string asmstr, string asmstr2,
132 InstrItinClass itin>:
133 FEXT_I816<_func, (outs),
134 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
135 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
136 !strconcat(asmstr, "\t$imm"))),[], itin> {
143 class FEXT_T8I8I16_ins<bits<3> _func, string asmstr, string asmstr2,
144 InstrItinClass itin>:
145 FEXT_I816<_func, (outs),
146 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
147 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
148 !strconcat(asmstr, "\t$targ"))), [], itin> {
155 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
157 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
158 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32),
159 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
162 // I8_MOV32R instruction format (used only by MOV32R instruction)
165 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
166 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
167 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
170 // This are pseudo formats for multiply
171 // This first one can be changed to non pseudo now.
175 class FMULT16_ins<string asmstr, InstrItinClass itin> :
176 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
177 !strconcat(asmstr, "\t$rx, $ry"), []>;
182 class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
183 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
184 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
189 // RR-type instruction format
192 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
193 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
194 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
198 // maybe refactor but need a $zero as a dummy first parameter
200 class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
201 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
202 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
204 class FRR16_M_ins<bits<5> f, string asmstr,
205 InstrItinClass itin> :
206 FRR16<f, (outs CPU16Regs:$rx), (ins),
207 !strconcat(asmstr, "\t$rx"), [], itin>;
209 class FRxRxRy16_ins<bits<5> f, string asmstr,
210 InstrItinClass itin> :
211 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
212 !strconcat(asmstr, "\t$rz, $ry"),
214 let Constraints = "$rx = $rz";
218 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
219 string asmstr, InstrItinClass itin>:
220 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
224 // RRR-type instruction format
227 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
228 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
229 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
232 // Some general instruction class info
236 class ArithLogic16Defs<bit isCom=0> {
238 bit isCommutable = isCom;
239 bit isReMaterializable = 1;
240 bit neverHasSideEffects = 1;
245 bit isTerminator = 1;
251 bit isTerminator = 1;
263 // Format: ADDIU rx, immediate MIPS16e
264 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
265 // To add a constant to a 32-bit integer.
267 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
269 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
274 // Format: ADDIU rx, pc, immediate MIPS16e
275 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
276 // To add a constant to the program counter.
278 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
280 // Format: ADDU rz, rx, ry MIPS16e
281 // Purpose: Add Unsigned Word (3-Operand)
282 // To add 32-bit integers.
285 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
288 // Format: AND rx, ry MIPS16e
290 // To do a bitwise logical AND.
292 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
296 // Format: BEQZ rx, offset MIPS16e
297 // Purpose: Branch on Equal to Zero (Extended)
298 // To test a GPR then do a PC-relative conditional branch.
300 def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
302 // Format: B offset MIPS16e
303 // Purpose: Unconditional Branch
304 // To do an unconditional PC-relative branch.
306 def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
309 // Format: BNEZ rx, offset MIPS16e
310 // Purpose: Branch on Not Equal to Zero (Extended)
311 // To test a GPR then do a PC-relative conditional branch.
313 def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
316 // Format: BTEQZ offset MIPS16e
317 // Purpose: Branch on T Equal to Zero (Extended)
318 // To test special register T then do a PC-relative conditional branch.
320 def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16;
322 def BteqzT8CmpX16: FEXT_T8I816_ins<0b000, "bteqz", "cmp", IIAlu>, cbranch16;
324 def BteqzT8CmpiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "cmpi", IIAlu>,
327 def BteqzT8SltX16: FEXT_T8I816_ins<0b000, "bteqz", "slt", IIAlu>, cbranch16;
329 def BteqzT8SltuX16: FEXT_T8I816_ins<0b000, "bteqz", "sltu", IIAlu>, cbranch16;
331 def BteqzT8SltiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "slti", IIAlu>, cbranch16;
333 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<0b000, "bteqz", "sltiu", IIAlu>,
337 // Format: BTNEZ offset MIPS16e
338 // Purpose: Branch on T Not Equal to Zero (Extended)
339 // To test special register T then do a PC-relative conditional branch.
341 def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16;
343 def BtnezT8CmpX16: FEXT_T8I816_ins<0b000, "btnez", "cmp", IIAlu>, cbranch16;
345 def BtnezT8CmpiX16: FEXT_T8I8I16_ins<0b000, "btnez", "cmpi", IIAlu>, cbranch16;
347 def BtnezT8SltX16: FEXT_T8I816_ins<0b000, "btnez", "slt", IIAlu>, cbranch16;
349 def BtnezT8SltuX16: FEXT_T8I816_ins<0b000, "btnez", "sltu", IIAlu>, cbranch16;
351 def BtnezT8SltiX16: FEXT_T8I8I16_ins<0b000, "btnez", "slti", IIAlu>, cbranch16;
353 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<0b000, "btnez", "sltiu", IIAlu>,
357 // Format: DIV rx, ry MIPS16e
358 // Purpose: Divide Word
359 // To divide 32-bit signed integers.
361 def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
366 // Format: DIVU rx, ry MIPS16e
367 // Purpose: Divide Unsigned Word
368 // To divide 32-bit unsigned integers.
370 def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
376 // Format: JR ra MIPS16e
377 // Purpose: Jump Register Through Register ra
378 // To execute a branch to the instruction address in the return
382 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu>;
385 // Format: LB ry, offset(rx) MIPS16e
386 // Purpose: Load Byte (Extended)
387 // To load a byte from memory as a signed value.
389 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad;
392 // Format: LBU ry, offset(rx) MIPS16e
393 // Purpose: Load Byte Unsigned (Extended)
394 // To load a byte from memory as a unsigned value.
396 def LbuRxRyOffMemX16:
397 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad;
400 // Format: LH ry, offset(rx) MIPS16e
401 // Purpose: Load Halfword signed (Extended)
402 // To load a halfword from memory as a signed value.
404 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad;
407 // Format: LHU ry, offset(rx) MIPS16e
408 // Purpose: Load Halfword unsigned (Extended)
409 // To load a halfword from memory as an unsigned value.
411 def LhuRxRyOffMemX16:
412 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad;
415 // Format: LI rx, immediate MIPS16e
416 // Purpose: Load Immediate (Extended)
417 // To load a constant into a GPR.
419 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
422 // Format: LW ry, offset(rx) MIPS16e
423 // Purpose: Load Word (Extended)
424 // To load a word from memory as a signed value.
426 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad;
428 // Format: LW rx, offset(sp) MIPS16e
429 // Purpose: Load Word (SP-Relative, Extended)
430 // To load an SP-relative word from memory as a signed value.
432 def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad;
435 // Format: MOVE r32, rz MIPS16e
437 // To move the contents of a GPR to a GPR.
439 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
442 // Format: MOVE ry, r32 MIPS16e
444 // To move the contents of a GPR to a GPR.
446 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
449 // Format: MFHI rx MIPS16e
450 // Purpose: Move From HI Register
451 // To copy the special purpose HI register to a GPR.
453 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
455 let neverHasSideEffects = 1;
459 // Format: MFLO rx MIPS16e
460 // Purpose: Move From LO Register
461 // To copy the special purpose LO register to a GPR.
463 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
465 let neverHasSideEffects = 1;
469 // Pseudo Instruction for mult
471 def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
472 let isCommutable = 1;
473 let neverHasSideEffects = 1;
477 def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
478 let isCommutable = 1;
479 let neverHasSideEffects = 1;
484 // Format: MULT rx, ry MIPS16e
485 // Purpose: Multiply Word
486 // To multiply 32-bit signed integers.
488 def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
489 let isCommutable = 1;
490 let neverHasSideEffects = 1;
495 // Format: MULTU rx, ry MIPS16e
496 // Purpose: Multiply Unsigned Word
497 // To multiply 32-bit unsigned integers.
499 def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
500 let isCommutable = 1;
501 let neverHasSideEffects = 1;
506 // Format: NEG rx, ry MIPS16e
508 // To negate an integer value.
510 def NegRxRy16: FRR16_ins<0b11101, "neg", IIAlu>;
513 // Format: NOT rx, ry MIPS16e
515 // To complement an integer value
517 def NotRxRy16: FRR16_ins<0b01111, "not", IIAlu>;
520 // Format: OR rx, ry MIPS16e
522 // To do a bitwise logical OR.
524 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
527 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
528 // (All args are optional) MIPS16e
529 // Purpose: Restore Registers and Deallocate Stack Frame
530 // To deallocate a stack frame before exit from a subroutine,
531 // restoring return address and static registers, and adjusting
535 // fixed form for restoring RA and the frame
536 // for direct object emitter, encoding needs to be adjusted for the
539 let ra=1, s=0,s0=1,s1=1 in
541 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
542 "restore \t$$ra, $$s0, $$s1, $frame_size", [], IILoad >, MayLoad {
543 let isCodeGenOnly = 1;
547 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
549 // Purpose: Save Registers and Set Up Stack Frame
550 // To set up a stack frame on entry to a subroutine,
551 // saving return address and static registers, and adjusting stack
553 let ra=1, s=1,s0=1,s1=1 in
555 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
556 "save \t$$ra, $$s0, $$s1, $frame_size", [], IIStore >, MayStore {
557 let isCodeGenOnly = 1;
560 // Format: SB ry, offset(rx) MIPS16e
561 // Purpose: Store Byte (Extended)
562 // To store a byte to memory.
565 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
568 // Format: SH ry, offset(rx) MIPS16e
569 // Purpose: Store Halfword (Extended)
570 // To store a halfword to memory.
573 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore;
576 // Format: SLL rx, ry, sa MIPS16e
577 // Purpose: Shift Word Left Logical (Extended)
578 // To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
580 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
583 // Format: SLLV ry, rx MIPS16e
584 // Purpose: Shift Word Left Logical Variable
585 // To execute a left-shift of a word by a variable number of bits.
587 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
590 // Format: SLTI rx, immediate MIPS16e
591 // Purpose: Set on Less Than Immediate (Extended)
592 // To record the result of a less-than comparison with a constant.
594 def SltiCCRxImmX16: FEXT_CCRXI16_ins<0b01010, "slti", IIAlu>;
597 // Format: SLTIU rx, immediate MIPS16e
598 // Purpose: Set on Less Than Immediate Unsigned (Extended)
599 // To record the result of a less-than comparison with a constant.
601 def SltiuCCRxImmX16: FEXT_CCRXI16_ins<0b01011, "sltiu", IIAlu>;
604 // Format: SLT rx, ry MIPS16e
605 // Purpose: Set on Less Than
606 // To record the result of a less-than comparison.
608 def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>;
610 def SltCCRxRy16: FCCRR16_ins<0b00010, "slt", IIAlu>;
612 // Format: SLTU rx, ry MIPS16e
613 // Purpose: Set on Less Than Unsigned
614 // To record the result of an unsigned less-than comparison.
618 def SltuCCRxRy16: FCCRR16_ins<0b00011, "sltu", IIAlu>;
620 // Format: SRAV ry, rx MIPS16e
621 // Purpose: Shift Word Right Arithmetic Variable
622 // To execute an arithmetic right-shift of a word by a variable
625 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
629 // Format: SRA rx, ry, sa MIPS16e
630 // Purpose: Shift Word Right Arithmetic (Extended)
631 // To execute an arithmetic right-shift of a word by a fixed
632 // number of bits—1 to 8 bits.
634 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
638 // Format: SRLV ry, rx MIPS16e
639 // Purpose: Shift Word Right Logical Variable
640 // To execute a logical right-shift of a word by a variable
643 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
647 // Format: SRL rx, ry, sa MIPS16e
648 // Purpose: Shift Word Right Logical (Extended)
649 // To execute a logical right-shift of a word by a fixed
650 // number of bits—1 to 31 bits.
652 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
655 // Format: SUBU rz, rx, ry MIPS16e
656 // Purpose: Subtract Unsigned Word
657 // To subtract 32-bit integers
659 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
662 // Format: SW ry, offset(rx) MIPS16e
663 // Purpose: Store Word (Extended)
664 // To store a word to memory.
667 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore;
670 // Format: SW rx, offset(sp) MIPS16e
671 // Purpose: Store Word rx (SP-Relative)
672 // To store an SP-relative word to memory.
674 def SwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b11010, "sw", IIStore>, MayStore;
678 // Format: XOR rx, ry MIPS16e
680 // To do a bitwise logical XOR.
682 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
684 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
685 let Predicates = [InMips16Mode];
690 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
691 Mips16Pat<(OpNode CPU16Regs:$r),
694 def: ArithLogicU_pat<not, NotRxRy16>;
695 def: ArithLogicU_pat<ineg, NegRxRy16>;
697 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
698 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
699 (I CPU16Regs:$l, CPU16Regs:$r)>;
701 def: ArithLogic16_pat<add, AdduRxRyRz16>;
702 def: ArithLogic16_pat<and, AndRxRxRy16>;
703 def: ArithLogic16_pat<mul, MultRxRyRz16>;
704 def: ArithLogic16_pat<or, OrRxRxRy16>;
705 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
706 def: ArithLogic16_pat<xor, XorRxRxRy16>;
708 // Arithmetic and logical instructions with 2 register operands.
710 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
711 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
712 (I CPU16Regs:$in, imm_type:$imm)>;
714 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
715 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
716 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
717 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
719 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
720 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
721 (I CPU16Regs:$r, CPU16Regs:$ra)>;
723 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
724 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
725 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
727 class LoadM16_pat<PatFrag OpNode, Instruction I> :
728 Mips16Pat<(OpNode addr:$addr), (I addr:$addr)>;
730 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
731 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
732 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
733 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
734 def: LoadM16_pat<load, LwRxRyOffMemX16>;
736 class StoreM16_pat<PatFrag OpNode, Instruction I> :
737 Mips16Pat<(OpNode CPU16Regs:$r, addr:$addr), (I CPU16Regs:$r, addr:$addr)>;
739 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
740 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
741 def: StoreM16_pat<store, SwRxRyOffMemX16>;
743 // Unconditional branch
744 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
745 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
746 let Predicates = [RelocPIC, InMips16Mode];
749 // Jump and Link (Call)
750 let isCall=1, hasDelaySlot=1 in
752 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
753 "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
756 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
757 hasExtraSrcRegAllocReq = 1 in
758 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
763 class SetCC_R16<PatFrag cond_op, Instruction I>:
764 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
765 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
767 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
768 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
769 (I CPU16Regs:$rx, imm_type:$imm16)>;
773 // Some branch conditional patterns are not generated by llvm at this time.
774 // Some are for seemingly arbitrary reasons not used: i.e. with signed number
775 // comparison they are used and for unsigned a different pattern is used.
776 // I am pushing upstream from the full mips16 port and it seemed that I needed
777 // these earlier and the mips32 port has these but now I cannot create test
778 // cases that use these patterns. While I sort this all out I will leave these
779 // extra patterns commented out and if I can be sure they are really not used,
780 // I will delete the code. I don't want to check the code in uncommented without
781 // a valid test case. In some cases, the compiler is generating patterns with
782 // setcc instead and earlier I had implemented setcc first so may have masked
783 // the problem. The setcc variants are suboptimal for mips16 so I may wantto
784 // figure out how to enable the brcond patterns or else possibly new
785 // combinations of of brcond and setcc.
791 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
792 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
797 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
798 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
802 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
803 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16)
807 // bcond-setgt (do we need to have this pair of setlt, setgt??)
810 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
811 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
818 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
819 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
823 // never called because compiler transforms a >= k to a > (k-1)
825 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
826 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
833 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
834 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
838 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
839 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
846 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
847 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
854 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
855 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
859 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
860 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
864 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
865 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
869 // This needs to be there but I forget which code will generate it
872 <(brcond CPU16Regs:$rx, bb:$targ16),
873 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
882 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
883 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
890 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
891 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
899 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
900 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
903 def: UncondBranch16_pat<br, BimmX16>;
906 def: Mips16Pat<(i32 immSExt16:$in),
907 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
909 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
915 <(MipsDivRem CPU16Regs:$rx, CPU16Regs:$ry),
916 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
922 <(MipsDivRemU CPU16Regs:$rx, CPU16Regs:$ry),
923 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
927 // When writing C code to test setxx these patterns,
928 // some will be transformed into
929 // other things. So we test using C code but using -O3 and -O0
934 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
935 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
938 <(seteq CPU16Regs:$lhs, 0),
939 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
947 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
948 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
952 // For constants, llvm transforms this to:
953 // x > (k -1) and then reverses the operands to use setlt. So this pattern
954 // is not used now by the compiler. (Presumably checking that k-1 does not
955 // overflow). The compiler never uses this at a the current time, due to
956 // other optimizations.
959 // <(setge CPU16Regs:$lhs, immSExt16:$rhs),
960 // (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
963 // This catches the x >= -32768 case by transforming it to x > -32769
966 <(setgt CPU16Regs:$lhs, -32769),
967 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
976 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
977 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
983 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
984 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
989 def: SetCC_R16<setlt, SltCCRxRy16>;
991 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
997 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
998 (SltuCCRxRy16 (LiRxImmX16 0),
999 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
1006 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
1007 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1010 // this pattern will never be used because the compiler will transform
1011 // x >= k to x > (k - 1) and then use SLT
1014 // <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
1015 // (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
1016 // (LiRxImmX16 1))>;
1022 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
1023 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1029 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
1030 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1035 def: SetCC_R16<setult, SltuCCRxRy16>;
1037 def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
1039 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
1040 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;